vhdl.txt

有人用FPGA控制过液晶屏吗（vhdl)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity i2csyn is
port(
     clk,reset:in std_logic;
     scl:out std_logic;
     ack_i,exnt_ack:buffer std_logic;
    fi2c,fcore:buffer std_logic;
     sda:inout std_logic
    );
end i2csyn;
architecture behav of i2csyn is
component i2c_cmd
port(clk,reset,ack_i:      in std_logic;
     --datain:         in std_logic_vector(7 downto 0);
     --addr:           in std_logic_vector(1 downto 0);
     fi2c,fcore:       out std_logic;
     start_i,stop_i:     out std_logic;
     txreg:  out std_logic_vector(7 downto 0);
     exnt_ack:   in std_logic
     --exnt:buffer std_logic
    );

end component;
component top_start
port(
     reset,fcore,fi2c,start_i,stop_i:in std_logic;
     tx:in std_logic_vector(7 downto 0);
     exnt_ack:out std_logic;
     scl:out std_logic;
     ack_i: buffer std_logic;
     sda:inout std_logic
     );
end component;
signal start_i,stop_i:std_logic;
signal tx:std_logic_vector(7 downto 0);
begin
t1:i2c_cmd port map(clk,reset,ack_i,fi2c,fcore,start_i,stop_i,tx,exnt_ack);
t2:top_start port map(reset,fcore,fi2c,start_i,stop_i,tx,exnt_ack,scl,ack_i,sda);
end behav;

port(clk :in std_logic;
    datalcm:inout std_logic_vector(7 downto 0);--数据口
    rwlcm,dilcm,elcm,cs1lcm,cs2lcm:out std_logic);
end ;
architecture behav of write is
signal cnt:integer range 0 to 12 :=0;
signal cs : bit:='0';
begin
process(clk)
begin
if clk'event and clk='1' then
  if cnt=12 then cnt<=0;
  else cnt<=cnt+1;
  end if;
  if cs='0' then --写128×64显示屏的左半屏
    if cnt=0 then 
    elcm<='0';rwlcm<='0';cs1lcm<='1';cs2lcm<='0';dilcm<='0';
    elsif cnt=5 then elcm<='1';datalcm<="00111111";
    elsif cnt=10 then elcm<='0';
    elsif cnt=11 then rwlcm<='1';cs<='1';
    end if;
  else  --写128×64显示屏的右半屏
    if cnt=0 then 
    elcm<='0';rwlcm<='0';cs1lcm<='0';cs2lcm<='1';dilcm<='0';
    elsif cnt=5 then elcm<='1';datalcm<="00111111";
    elsif cnt=10 then elcm<='0';
    elsif cnt=11 then rwlcm<='1';cs<='0';
    end if;
end if;
end if;
end process;