vhdl.txt

自编自写的ＶＨＤＬ代码

三人表决器BEGIN
   --component instantiation statements. 
   --ports of component are mapped to signals 
   --within architecture by position.
   gate1 : and2 PORT MAP (a, b, w1);
   gate2 : and2 PORT MAP (b, c, w2);      
   gate3 : and2 PORT MAP (a, c, w3);      
   gate4 : or3 PORT MAP (w1, w2, w3, m);      
END structure;

--Behavioural style architecture using a look-up table
ARCHITECTURE using_table OF maj IS
BEGIN
   PROCESS(a,b,c)
      CONSTANT lookuptable : BIT_VECTOR(0 TO 7) := "00010111";
      VARIABLE index : NATURAL;
   BEGIN
      index := 0; --index must be cleared each time process executes
      IF a = '1' THEN index := index + 1; END IF;
      IF b = '1' THEN index := index + 2; END IF;
      IF c = '1' THEN index := index + 4; END IF;
      m <= lookuptable(index);
   END PROCESS;
END using_table;
（三种不同的描述方式）
8位总线收发器：74245
library IEEE;   
use IEEE.Std_logic_1164.all;

entity HCT245 is
   port(A, B : inout std_logic_vector(7 downto 0);
         DIR, GBAR : in std_logic);
end HCT245;

architecture VER1 of HCT245 is
begin
   A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');
   B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');
end VER1;
地址译码（for m68008）
library ieee;
use ieee.std_logic_1164.all;
entity addrdec is
        port(
        asbar : in std_logic; 
        address : in std_logic_vector(19 downto 0);
        csbar : out std_logic_vector(3 downto 0)
        );
end entity addrdec;


architecture v1 of addrdec is
begin

        csbar(0) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"00000") and (address <=  X"01FFF"))) 
                else '1';
                                                                
        csbar(1) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"40000") and (address <=  X"43FFF"))) 
                else '1';
                                                                
        csbar(2) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"08000") and (address <=  X"0AFFF"))) 
                else '1';
                                                                
        csbar(3) <= '0' when 
                ((asbar  = '0') and 
                ((address >=  X"E0000") and (address <=  X"E01FF"))) 
                else '1';               
                                                                                                                                                                                
end architecture v1;
多路选择器（使用select语句）
library ieee;
use ieee.std_logic_1164.all;

entity mux is port(
        a, b, c, d:     in std_logic_vector(3 downto 0);
        s:              in std_logic_vector(1 downto 0);
        x:              out std_logic_vector(3 downto 0));
end mux;

architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
        begin
                if s = "00" then
                        x <= a; 
                elsif s = "01" then
                        x <= b;
                elsif s = "10" then
                        x <= c;
                else
                        x <= d;
                end if;
        end process mux4_1;
end archmux;
LED七段译码
library IEEE;
use IEEE.std_logic_1164.all;

entity bin27seg is
	port (
		data_in : in std_logic_vector (3 downto 0);
		EN : in std_logic;
		data_out : out std_logic_vector (6 downto 0)
	);
end entity;



architecture bin27seg_arch of bin27seg is
begin

	process(data_in, EN)
	begin
		data_out <= (others => '1');
		if EN='1' then
			case data_in is
				when "0000" => data_out <= "1000000"; -- 0
				when "0001" => data_out <= "1111001"; -- 1
				when "0010" => data_out <= "0100100"; -- 2
				when "0011" => data_out <= "0110000"; -- 3
				when "0100" => data_out <= "0011001"; -- 4
				when "0101" => data_out <= "0010010"; -- 5
				when "0110" => data_out <= "0000011"; -- 6
				when "0111" => data_out <= "1111000"; -- 7
				when "1000" => data_out <= "0000000"; -- 8
				when "1001" => data_out <= "0011000"; -- 9
				when "1010" => data_out <= "0001000"; -- A
				when "1011" => data_out <= "0000011"; -- b
				when "1100" => data_out <= "0100111"; -- c
				when "1101" => data_out <= "0100001"; -- d
				when "1110" => data_out <= "0000110"; -- E
				when "1111" => data_out <= "0001110"; -- F
				when others => NULL;
			end case;
		end if;
	end process;

end architecture;
多路选择器（使用if－else语句）
library ieee;
use ieee.std_logic_1164.all;

entity mux is port(
        a, b, c, d:     in std_logic_vector(3 downto 0);
        s:              in std_logic_vector(1 downto 0);
        x:              out std_logic_vector(3 downto 0));
end mux;

architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
        begin
                if s = "00" then
                        x <= a; 
                elsif s = "01" then
                        x <= b;
                elsif s = "10" then
                        x <= c;
                else
                        x <= d;
                end if;
        end process mux4_1;
end archmux;
双2－4译码器：74139
library IEEE;
use IEEE.Std_logic_1164.all;


entity HCT139 is  
   port(A2, B2, G2BAR, A1, B1, G1BAR : in std_logic;
            Y20, Y21, Y22, Y23, Y10, Y11, Y12, Y13 : out std_logic);
end HCT139;

architecture VER1 of HCT139 is
begin
   Y10 <= '0' when (B1 = '0') and ((A1 = '0') and (G1BAR = '0')) else '1';  
   Y11 <= '0' when (B1 = '0') and ((A1 = '1') and (G1BAR = '0')) else '1';
   Y12 <= '0' when (B1 = '1') and ((A1 = '0') and (G1BAR = '0')) else '1';
   Y13 <= '0' when (B1 = '1') and ((A1 = '1') and (G1BAR = '0')) else '1';
   Y20 <= '0' when (B2 = '0') and ((A2 = '0') and (G2BAR = '0')) else '1';  
   Y21 <= '0' when (B2 = '0') and ((A2 = '1') and (G2BAR = '0')) else '1';
   Y22 <= '0' when (B2 = '1') and ((A2 = '0') and (G2BAR = '0')) else '1';
   Y23 <= '0' when (B2 = '1') and ((A2 = '1') and (G2BAR = '0')) else '1';
多路选择器（使用when－else语句）
library ieee;
use ieee.std_logic_1164.all;

entity mux is port(
        a, b, c, d:     in std_logic_vector(3 downto 0);
        s:              in std_logic_vector(1 downto 0);
        x:              out std_logic_vector(3 downto 0));
end mux;

architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
        begin
                if s = "00" then
                        x <= a; 
                elsif s = "01" then
                        x <= b;
                elsif s = "10" then
                        x <= c;
                else
                        x <= d;
                end if;
        end process mux4_1;
end archmux;
二进制到BCD码转换
library IEEE;
use IEEE.std_logic_1164.all;

entity bin2bcd is
	port(
		data_in : in std_logic_vector(3 downto 0);
		EN : in std_logic;
		data_out : out std_logic_vector(7 downto 0)
	);
end entity;


architecture bin2bcd of bin2bcd is
begin

	process(data_in, EN)
	variable data_in_TEMP : std_logic_vector(2 downto 0);
	begin
		data_in_TEMP := data_in(3 downto 1);
		data_out <= (others => '0');
		if EN='1' then
			case data_in_TEMP is
				when "000" => data_out(7 downto 1) <= "0000000";
				when "001" => data_out(7 downto 1) <= "0000001";
				when "010" => data_out(7 downto 1) <= "0000010";
				when "011" => data_out(7 downto 1) <= "0000011";
				when "100" => data_out(7 downto 1) <= "0000100";
				when "101" => data_out(7 downto 1) <= "0001000";
				when "110" => data_out(7 downto 1) <= "0001001";
				when "111" => data_out(7 downto 1) <= "0001010";
				when others => data_out <= (others => '0');
			end case;

			data_out(0) <= data_in(0);
		end if;
	end process;

end architecture;
多路选择器 （使用case语句）
library ieee;
use ieee.std_logic_1164.all;

entity mux is port(
        a, b, c, d:     in std_logic_vector(3 downto 0);
        s:              in std_logic_vector(1 downto 0);
        x:              out std_logic_vector(3 downto 0));
end mux;

architecture archmux of mux is
begin
mux4_1: process (a, b, c, d)
        begin
                if s = "00" then
                        x <= a; 
                elsif s = "01" then
                        x <= b;
                elsif s = "10" then
                        x <= c;
                else
                        x <= d;
                end if;
        end process mux4_1;
end archmux;