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找到约 10,000 项符合
VHDL 的代码
100vhdl+
--以下是部件声明的包
--部件mem_sequence,mem_string，以及协处理器分别在以下的包pkg_components中进行了说明
--每一个内存块中包括一个局部控制器，该局部控制器管理一个双向端口的RAM
--其中26-36行是mem_sequence的
--73-83行是mem_string的
--实际上每一个双端RAM都将其自己封装为真正的RAM部件
LIBR
100vhdl+
--LIBRARY synergy;
-- USE synergy.signed_arith.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
-- USE ieee.std_logic_signed.all;
-- USE synergy.signed_arit
100vhdl+
--这是子类型和部件声明的包
--用于区分向量类型的不同宽度
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
PACKAGE pkg_types IS
SUBTYPE bit1 IS std_ulogic;
SUBTYPE bit
vhdl.vhd
-- generated by newgenasym Fri Mar 16 13:12:38 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity BNC_CONN is
port (
AGND1: INOUT STD_LOGIC;
AGND2: IN
vhdl.vhd
-- generated by newgenasym Fri Mar 16 13:33:15 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity INDUCTOR is
port (
A: INOUT STD_LOGIC;
B: IN
vhdl.vhd
-- generated by newgenasym Fri Mar 16 11:48:43 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity RES is
port (
A: INOUT STD_LOGIC;
B: INOUT
vhdl.vhd
-- generated by newgenasym Thu Mar 22 14:14:15 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity \20l10\ is
port (
I1: IN STD_LOGIC;
I10: IN
vhdl.vhd
-- generated by newgenasym Thu Mar 22 14:40:16 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity TC55B4257 is
port (
A0: IN STD_LOGIC;
A1: I
vhdl.vhd
-- generated by newgenasym Thu Mar 22 14:41:46 2001
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity TLC5602 is
port (
AGND1: INOUT STD_LOGIC;
AOUT: INO