vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 14:14:15 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \20l10\ is
    port (    
	I1:        IN     STD_LOGIC;    
	I10:       IN     STD_LOGIC;    
	I11:       IN     STD_LOGIC;    
	I12:       IN     STD_LOGIC;    
	I2:        IN     STD_LOGIC;    
	I3:        IN     STD_LOGIC;    
	I4:        IN     STD_LOGIC;    
	I5:        IN     STD_LOGIC;    
	I6:        IN     STD_LOGIC;    
	I7:        IN     STD_LOGIC;    
	I8:        IN     STD_LOGIC;    
	I9:        IN     STD_LOGIC;    
	O1:        OUT    STD_LOGIC;    
	O10:       OUT    STD_LOGIC;    
	O2:        OUT    STD_LOGIC;    
	O3:        OUT    STD_LOGIC;    
	O4:        OUT    STD_LOGIC;    
	O5:        OUT    STD_LOGIC;    
	O6:        OUT    STD_LOGIC;    
	O7:        OUT    STD_LOGIC;    
	O8:        OUT    STD_LOGIC;    
	O9:        OUT    STD_LOGIC);
end \20l10\;