vhdl.vhd

cadence公司pcb内部培训的资料,并且附带其中的例子程序!比市面上任何一本cadence的书好!

-- generated by newgenasym Thu Mar 22 14:40:16 2001

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity TC55B4257 is
    port (    
	A0:        IN     STD_LOGIC;    
	A1:        IN     STD_LOGIC;    
	A10:       IN     STD_LOGIC;    
	A11:       IN     STD_LOGIC;    
	A12:       IN     STD_LOGIC;    
	A13:       IN     STD_LOGIC;    
	A14:       IN     STD_LOGIC;    
	A15:       IN     STD_LOGIC;    
	A16:       IN     STD_LOGIC;    
	A17:       IN     STD_LOGIC;    
	A2:        IN     STD_LOGIC;    
	A3:        IN     STD_LOGIC;    
	A4:        IN     STD_LOGIC;    
	A5:        IN     STD_LOGIC;    
	A6:        IN     STD_LOGIC;    
	A7:        IN     STD_LOGIC;    
	A8:        IN     STD_LOGIC;    
	A9:        IN     STD_LOGIC;    
	\ce*\:     IN     STD_LOGIC;    
	DQ1:       INOUT  STD_LOGIC;    
	DQ2:       INOUT  STD_LOGIC;    
	DQ3:       INOUT  STD_LOGIC;    
	DQ4:       INOUT  STD_LOGIC;    
	\eo*\:     IN     STD_LOGIC;    
	IO1:       INOUT  STD_LOGIC;    
	IO2:       INOUT  STD_LOGIC;    
	IO3:       INOUT  STD_LOGIC;    
	\we*\:     IN     STD_LOGIC);
end TC55B4257;