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VHDL 的代码
fenpin.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
display.vhdl
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for ins
vhdl.scr
/* link TOP design */
read COMPUTE_BLOCK.db
read CONVERTOR_CKT.db
read -format vhdl TOP.vhd
current_design TOP
link
/* testability analysis */
set_test_hold 1 TEST_MODE
set_test_methodology full_scan
vhdl.scr
/* optimize CONVERTOR_CKT */
read -format pla vhdl/CONVERTOR.pla
read -format vhdl vhdl/CONVERTOR_CKT.vhd
current_design CONVERTOR_CKT
set_scan_style combinational
uniquify
compile
/* testability ana
vhdl.csh
#! /bin/csh
cd library
mkdir src
mkdir FTGS
cd src
liban -arch FTGS -xgen ../class.db
ls
vhdlan -w class class_FTGS.vhd.E class_components.vhd
cd ../..
vhdlan alarm_clock.vhd
vhdlan tb_alarm.vhd
vhd
.script_vhdl
read -f pla vhdl/CONVERTOR.pla
read -f vhdl vhdl/CONVERTOR_CKT.vhd
current_design CONVERTOR_CKT
link
set_scan_configuration -style combinational
uniquify
compile
check_test
create_test_patterns -samp
vhdl.txt
5-1