📄 .script_vhdl
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read -f pla vhdl/CONVERTOR.plaread -f vhdl vhdl/CONVERTOR_CKT.vhdcurrent_design CONVERTOR_CKTlinkset_scan_configuration -style combinationaluniquifycompilecheck_testcreate_test_patterns -sample 11read -f vhdl vhdl/ALARM_SM_2.vhdcurrent_design ALARM_SM_2linkcreate_clock CLOCK -period 50 -waveform {0 25}set_max_area 0 set_scan_configuration -style multiplexed_flip_flop compile -scancheck_testpreview_scaninsert_scancheck_testread -f vhdl vhdl/COMPARATOR.vhdcurrent_design COMPARATORlinkset_scan_configuration -style combinationalcompilecheck_testread -f vhdl vhdl/TIME_BLOCK.vhdcurrent_design TIME_BLOCKlinkcreate_clock CLK -period 50 -waveform {0 25}set_max_area 0 set_scan_configuration -style multiplexed_flip_flop compile -scancheck_testpreview_scaninsert_scancheck_testread -f vhdl vhdl/ALARM_BLOCK.vhdcurrent_design ALARM_BLOCKlinkcreate_clock CLK -period 50 -waveform {0 25}set_max_area 0 set_scan_configuration -style multiplexed_flip_flop compile -scancheck_testpreview_scaninsert_scancheck_testread -f vhdl vhdl/CLOCK_GEN.vhdcurrent_design CLOCK_GENlinkcreate_clock CLK -period 50 -waveform {0 25}set_max_area 0 set_scan_configuration -style multiplexed_flip_flop compile -scancheck_testpreview_scaninsert_scancheck_testread -format vhdl vhdl/COMPUTE_BLOCK.vhdcurrent_design COMPUTE_BLOCKlinkset_scan_configuration -style multiplexed_flip_flopcheck_testcreate_test_patternsremove_design {CLOCK_GEN COMPUTE_BLOCK}read -f vhdl .answers1/CLOCK_GEN.vhdread -f vhdl .answers1/COMPUTE_BLOCK.vhdcurrent_design CLOCK_GENlinkcreate_clock CLK -period 50 -waveform {0 25}set_max_area 0 set_scan_configuration -style multiplexed_flip_flop compile -scancheck_testpreview_scaninsert_scancheck_testcurrent_design COMPUTE_BLOCKlinkset_scan_configuration -style multiplexed_flip_flopset_test_hold 1 TEST_MODEcheck_testpreview_scaninsert_scancheck_testcreate_test_patterns report_test -faults -class untestedread -f vhdl .answers2/TOP.vhdlinkset_test_hold 1 TEST_MODEset_scan_configuration -style multiplexed_flip_flopcheck_testcreate_test_patterns -sample 11report_test -atpg_conflictremove_design COMPUTE_BLOCKset_dont_touch find(design "*")read -format vhdl .answers2/COMPUTE_BLOCK.vhdlinkset_scan_configuration -style multiplexed_flip_flopset_scan_configuration -dedicated_scan_ports truecompileremove_attribute find(design "*") dont_touchset_test_hold 1 TEST_MODEcheck_testpreview_scaninsert_scancheck_testcurrent_design TOPlinkcheck_testcreate_test_patterns -sample 11set_scan_configuration -style multiplexed_flip_flopcreate_clock CLK -period 15 -waveform {0 7}set_max_area 0 set_input_delay -clock CLK 1 all_inputs() - find(port , "CLK")set_output_delay -clock CLK 1 all_outputs()set_scan_configuration -disable falsecheck_testpreview_scaninsert_scancheck_testreport_constraintscreate_test_patternsU1 = filter(find(cell "*"), "(@is_combinational == true)")U2 = filter(find(cell "*"), "(@is_sequential == true)")U3 = filter(find(cell "*"), "(@is_hierarchical == true)")U4 = filter(find(cell "*"), "(@is_black_box == true)")group -design_name Core -cell_name Core {U1,U2,U3,U4}insert_jtagreport_test -portreport_test -jtagcheck_testcreate_test_patternsreport_test -coverage⌨️ 快捷键说明
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