vhdl.scr

design compile synthesis user guide

/* optimize CONVERTOR_CKT */
read -format pla vhdl/CONVERTOR.pla
read -format vhdl vhdl/CONVERTOR_CKT.vhd
current_design CONVERTOR_CKT
set_scan_style combinational
uniquify
compile

/* testability analysis */
check_test
create_test_patterns -sample 11

/* save CONVERTOR_CKT */
write -hier -out CONVERTOR_CKT.db


/* optimize ALARM_SM_2 without test-smart compile */
read -format vhdl vhdl/ALARM_SM_2.vhd
current_design ALARM_SM_2
create_clock CLK -period 15
max_area 0
write -hier -out unmapped_ALARM_SM_2.db
compile

/* testability analysis */
set_test_methodology full_scan
set_scan_style multiplexed_flip_flop
check_test
check_test -verbose
create_test_patterns -sample 11

remove_design find(design "*")

/* optimize ALARM_SM_2 using test-smart compile */
read unmapped_ALARM_SM_2.db
set_scan_style multiplexed_flip_flop
compile

/* testability analysis */
set_test_methodology full_scan
check_test

remove_design find(design "*")

/* process entire COMPUTE_BLOCK */
read vhdl/COMPUTE_BLOCK.db
current_design COMPUTE_BLOCK

/* testability analysis */
set_test_methodology full_scan
set_scan_style multiplexed_flip_flop
check_test
create_test_patterns -sample 11

/* optimize designs with test mode fix */
remove_design {CLOCK_GEN COMPUTE_BLOCK}
write find(design "*") -out save.db

read -format vhdl CLOCK_GEN.vhd
create_clock CLK -period 15
max_area 0
set_scan_style multiplexed_flip_flop
compile

read -format vhdl COMPUTE_BLOCK.vhd
read save.db
current_design COMPUTE_BLOCK

set_test_hold 1 TEST_MODE
check_test
create_test_patterns -sample 11
create_test_patterns
report_test -faults -class untested

write -hier -out COMPUTE_BLOCK.db
exit