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UART 的代码
uart.par
Release 7.1.01i par H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
HXS:: Fri Mar 25 09:03:53 2005
par -w -intstyle ise -ol std -t 1 uart_map.ncd uart.ncd uart.pcf
Constraints fi
uart.ncd
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.4
###5708:XlxV32DM 3fff 1634eNqtWmtz27bS/iv94A/N8dQhAJIAiTQTWbdwIks+kpzY50M5okh1/DaVcxznTDtR/NvfXVxIkITcJJNpDe4+e8ECzxKkFJ0wxj4TIk+W1f9uP97e7dOfyBkJfz
uart.prj
vhdl work "uart.vhd"
uart.vhd
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07:12:43 03/25/05
-- Design Name:
-- Module Name: uart - B
uart.ut
-w
-g DebugBitstream:No
-g Binary:no
-g Gclkdel0:11111
-g Gclkdel1:11111
-g Gclkdel2:11111
-g Gclkdel3:11111
-g ConfigRate:4
-g CclkPin:PullUp
-g M0Pin:PullUp
-g M1Pin:PullUp
-g M2Pin:Pu
uart.syr
Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 1.09 s | Elapsed : 0.00 / 1.00 s
--> Parameter xsthdpdir set
uart.lso
work