uart.syr

总体演示程序DEMO_FPGA.rar

Release 7.1.01i - xst H.39
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: uart.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "uart.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "uart"
Output Format                      : NGC
Target Device                      : xc2s100e-6-pq208

---- Source Options
Top Module Name                    : uart
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : uart.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/DEMO_FPGA/uart.vhd" in Library work.
Entity <uart> compiled.
Entity <uart> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <uart> (Architecture <behavioral>).
WARNING:Xst:819 - "E:/DEMO_FPGA/uart.vhd" line 116: The following signals are missing in the process sensitivity list:
   clk.
INFO:Xst:1304 - Contents of register <con> in unit <uart> never changes during circuit operation. The register is replaced by logic.
Entity <uart> analyzed. Unit <uart> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <uart>.
    Related source file is "E:/DEMO_FPGA/uart.vhd".
WARNING:Xst:646 - Signal <con> is assigned but never used.
INFO:Xst:1799 - State st3 is never reached in FSM <current_state>.
INFO:Xst:1799 - State st3 is never reached in FSM <current_state1>.
    Found finite state machine <FSM_0> for signal <current_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | bclk (rising_edge)                             |
    | Clock enable       | $n0006 (positive)                              |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <current_state1>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (falling_edge)                             |
    | Power Up State     | st0                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <dout>.
    Found 1-bit register for signal <txd>.
    Found 3-bit comparator less for signal <$n0007> created at line 90.
    Found 3-bit comparator less for signal <$n0011> created at line 125.
    Found 11-bit comparator less for signal <$n0015> created at line 66.
    Found 11-bit comparator less for signal <$n0016> created at line 66.
    Found 13-bit comparator less for signal <$n0027> created at line 55.
    Found 13-bit comparator less for signal <$n0028> created at line 55.
    Found 11-bit adder for signal <$n0031> created at line 65.
    Found 13-bit adder for signal <$n0032> created at line 54.
    Found 3-bit adder for signal <$n0033> created at line 90.
    Found 3-bit adder for signal <$n0034> created at line 125.
    Found 1-bit register for signal <bclk>.
    Found 13-bit up counter for signal <c>.
    Found 3-bit register for signal <cnt>.
    Found 3-bit register for signal <cnt0>.
    Found 11-bit up counter for signal <d>.
    Found 1-bit register for signal <reg_tre>.
    Found 1-bit register for signal <tclk>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred  18 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   6 Comparator(s).
Unit <uart> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <FSM_1> on signal <current_state1[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00
 st1   | 01
 st2   | 11
 st3   | unreached
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <current_state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 st0   | 00
 st1   | 01
 st2   | 11
 st3   | unreached
-------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Adders/Subtractors               : 4
 11-bit adder                      : 1
 13-bit adder                      : 1
 3-bit adder                       : 2
# Counters                         : 2
 11-bit up counter                 : 1
 13-bit up counter                 : 1
# Registers                        : 18
 1-bit register                    : 16
 3-bit register                    : 2
# Comparators                      : 6
 11-bit comparator less            : 2
 13-bit comparator less            : 2
 3-bit comparator less             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uart> ...
Loading device for application Rf_Device from file '2s100e.nph' in environment E:/Program/EDA/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uart, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : uart.ngr
Top Level Output File Name         : uart
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO