uart.vhd

总体演示程序DEMO_FPGA.rar

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-- Company: 
-- Engineer:
--
-- Create Date:    07:12:43 03/25/05
-- Design Name:    
-- Module Name:    uart - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart is
    port (clk : in std_logic;
          en  : in std_logic_vector(4 downto 0);
		button : in std_logic;
		dout : out std_logic_vector(7 downto 0);
		txd : out std_logic;
		tre : in std_logic);
end uart;

architecture Behavioral of uart is

type state1 is (st0,st1,st2,st3);
signal current_state : state1;

type state is (st0,st1,st2,st3);
signal current_state1 : state;

signal reg_tre : std_logic;
signal bclk,tclk : std_logic;

begin
process(clk)
variable c : integer range 0 to 5208;
begin
   if rising_edge(clk) then c:=c+1;
      if c<2604 then bclk<='0';
	 elsif c<5208 then bclk<='1';
	 else c:=0;
	 end if;
   end if;
end process;
 
process(clk)
variable d : integer range 0 to 2000;
begin
   if rising_edge(clk) then d:=d+1;
      if d<1000 then tclk<='0';
	 elsif d<2000 then tclk<='1';
	 else d:=0;
	 end if;
   end if;
end process;

send:process(en,bclk)
variable cnt : integer range 0 to 7;
variable con : std_logic_vector(7 downto 0);
begin
   if en="10101" then
      if rising_edge(bclk) then
	    case current_state is
	    when st0=>
	               cnt:=0;con:="10011000";
	            if button='1' then
			     txd<='0';
			     current_state<=st1;
			  else
			     txd<='1';
			  end if;
	    when st1=>
	            txd<=con(cnt);
			  if cnt< 7 then cnt:=cnt+1;
			  else current_state<=st2;
			  end if;	    

         when st2=>
	               txd<='1';
			  if button='0' then
			     current_state<=st0;
			  end if;
	    when others=>
	            current_state<=st0;
	    end case;
     end if;
  end if;
end process;

process(tclk,tre)
begin
   if rising_edge(tclk) then
      reg_tre<=tre;
   end if;
end process;

receive:process(tclk,reg_tre)
variable cnt : integer range 0 to 7;
begin
   if falling_edge(clk) then
      case current_state1 is
	 when st0=>
	             cnt:=0;
	          if reg_tre='0' then 
			   current_state1<=st1;
			end if;
      when st1=>
               dout(cnt)<=reg_tre;
			if cnt<7 then cnt:=cnt+1;
			else current_state1<=st2;
			end if;
			
	 when st2=>
	          if reg_tre='1' then
			   current_state1<=st0;
			end if;
      when others=>
	          current_state1<=st0;
	 end case;
   end if;
end process;
			   	          
end Behavioral;