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Test 的代码
test.udo
-- ProjNav VHDL simulation template: Test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
test.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri Mar 27 16:34:15 涓?鍥芥爣鍑嗘椂闂? 2009
##
vlib work
vlog "EMIF_COM.v"
vlog "Test.tfw"
vlog "D:/EDA/Xilinx91i/verilo
test.ant
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
/////////////////////////////////////////////////////
test.jhd
MODULE Test
SUBMODULE EMIF_COM
INSTANCE UUT
test.tbw
version 3
E:/ISE_Prj/EMIF_COM/EMIF_COM.v
EMIF_COM
VERILOG
VERILOG
E:/ISE_Prj/EMIF_COM/Test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLKOUT2
5000000
test.m
t0=.15; % signal duration
ts=0.001; % sampling interval
% the message vector
m=[ones(1,t0/(3*ts)),-2*ones(1,t0/(3*ts)),zeros(1,t0/(3*ts)+1)];
m_hat=imag(hil
test.c
/*
* File Name: test.c
*
* Descriptions:
* The test code of buttons module driver.
*
* Author:
* Mike Lee
* Kernel Version: 2.6.20
*
* Update:
* - 2007.07.23 Mike Lee Crea
test.aspx
Test
test.html
IE_FLASH.CAB
test.cpp
#include "md5.h"
#include
int main() {
qDebug()