test.fdo

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri Mar 27 16:34:15 涓?鍥芥爣鍑嗘椂闂? 2009
##
vlib work
vlog  "EMIF_COM.v"
vlog  "Test.tfw"
vlog  "D:/EDA/Xilinx91i/verilog/src/glbl.v"
vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -lib work Test glbl
view wave
add wave *
add wave /glbl/GSR
do {Test.udo}
view structure
view signals
run 1000ns