test.tbw

实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口

version 3
E:/ISE_Prj/EMIF_COM/EMIF_COM.v
EMIF_COM
VERILOG
VERILOG
E:/ISE_Prj/EMIF_COM/Test.xwv
Clocked
-
-
1000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLKOUT2
5000000
5000000
2000000
2000000
20000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
AOE
CLKOUT2
ARE
CLKOUT2
AWE
CLKOUT2
CE
CLKOUT2
CE2
CLKOUT2
EXT_INT
CLKOUT2
LED_OUT
CLKOUT2
RST
CLKOUT2
TEA
CLKOUT2
TED
CLKOUT2
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
EXT_INT_DIFF
LED_OUT_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
CLKOUT2
RST
CE2
AOE
ARE
AWE
TEA
TED
LED_OUT
EXT_INT
SIGNAL_ORDER_END
DIFFERENTIAL_CLKS_BEGIN
DIFFERENTIAL_CLKS_END
DIVIDERS_BEGIN
DIVIDERS_END