代码搜索：Test
找到约 10,000 项符合「Test」的源代码
代码结果 10,000
www.eeworm.com/read/179626/9347901
prj test.prj
[Compiler Options]
Edit1=D:\icc\include\
Edit19=
Edit2=D:\icc\lib\
Edit8=
CheckBox1=0
CheckBox2=1
Edit3=
Edit4=
Edit13=
ComboBox1=0
ComboBox2=9
Edit9=16384
Edit10=1024
Edit20=512
RadioG
www.eeworm.com/read/179626/9347908
cof test.cof
www.eeworm.com/read/375806/9349224
pl test.pl
use strict;
$^W = 1; # warnings too
my ($testnr, $maxnr, $oknr);
BEGIN { $testnr = 1; $maxnr = 42; print "$testnr..$maxnr\n"; }
sub ok ($) {
if ($_[0]) {
print "ok ", $testnr++, "\n";
$
www.eeworm.com/read/179576/9350068
txt test.txt
first line
second line
third line
fourth line
fifth line
sixth line
seven line
eightth line
ninth line
tenth line.
www.eeworm.com/read/179576/9350077
txt test.txt
first line
second line
third line
fourth line
fifth line
sixth line
seven line
eightth line
ninth line
tenth line.
www.eeworm.com/read/375761/9350220
ant test.ant
-- F:\AA
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 17:07:08 2008
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSI
www.eeworm.com/read/375761/9350233
tbw test.tbw
www.eeworm.com/read/375761/9350257
udo test.udo
-- ProjNav VHDL simulation template: test.udo
-- You may edit this file after the line that starts with
-- '-- START' to customize your simulation
-- START user-defined simulation commands
www.eeworm.com/read/375761/9350292
fdo test.fdo
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Fri Oct 31 17:07:12 中国标准时间 2008
##
vlib work
vcom -93 -explicit bps.vhdl
vcom -93 -explicit xmit.vhdl
vcom -93 -e
www.eeworm.com/read/375761/9350325
vhw test.vhw
-- F:\AA
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 17:07:08 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Waveform
--