test.ant

xilinx环境下开发vhdl语言串行接口设计

-- F:\AA
-- VHDL Annotation Test Bench created by
-- HDL Bencher 6.1i
-- Fri Oct 31 17:07:08 2008

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test IS
END test;

ARCHITECTURE testbench_arch OF test IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "f:\aa\test.ano";
	COMPONENT serial
		PORT (
			rst : In  std_logic;
			clk : In  std_logic;
			npreq : In  std_logic;
			nprd : In  std_logic;
			npwr : In  std_logic;
			ioab : In  std_logic_vector (1 DOWNTO 0);
			iodb : InOut  std_logic_vector (7 DOWNTO 0);
			rxd : In  std_logic;
			txd : Out  std_logic
		);
	END COMPONENT;

	SIGNAL rst : std_logic;
	SIGNAL clk : std_logic;
	SIGNAL npreq : std_logic;
	SIGNAL nprd : std_logic;
	SIGNAL npwr : std_logic;
	SIGNAL ioab : std_logic_vector (1 DOWNTO 0);
	SIGNAL iodb : std_logic_vector (7 DOWNTO 0);
	SIGNAL rxd : std_logic;
	SIGNAL txd : std_logic;

BEGIN
	UUT : serial
	PORT MAP (
		rst => rst,
		clk => clk,
		npreq => npreq,
		nprd => nprd,
		npwr => npwr,
		ioab => ioab,
		iodb => iodb,
		rxd => rxd,
		txd => txd
	);

	PROCESS -- clock process for clk,
		VARIABLE TX_TIME : INTEGER :=0;

		PROCEDURE ANNOTATE_txd(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",txd,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, txd);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

		PROCEDURE ANNOTATE_iodb(
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			STD.TEXTIO.write(TX_LOC,string'("Annotate["));
			STD.TEXTIO.write(TX_LOC, TX_TIME);
			STD.TEXTIO.write(TX_LOC,string'(",iodb,"));
			IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, iodb);
			STD.TEXTIO.write(TX_LOC, string'("]"));
			TX_STR(TX_LOC.all'range) := TX_LOC.all;
			STD.TEXTIO.writeline(results, TX_LOC);
			STD.TEXTIO.Deallocate(TX_LOC);
		END;

	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		clk <= transport '1';
		WAIT FOR 10 ns;
		TX_TIME := TX_TIME + 10;
		ANNOTATE_txd(TX_TIME);
		ANNOTATE_iodb(TX_TIME);
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		clk <= transport '0';
		WAIT FOR 40 ns;
		TX_TIME := TX_TIME + 40;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;

		BEGIN
		-- --------------------
		rst <= transport '0';
		npreq <= transport '0';
		nprd <= transport '0';
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		rst <= transport '1';
		npreq <= transport '1';
		nprd <= transport '1';
		ioab <= transport std_logic_vector'("00"); --0
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		npwr <= transport '0';
		ioab <= transport std_logic_vector'("00"); --0
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		npwr <= transport '0';
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 200 ns; -- Time=500 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 200 ns; -- Time=900 ns
		rxd <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		rxd <= transport '0';
		-- --------------------
		WAIT FOR 810 ns; -- Time=1810 ns
		-- --------------------

		STD.TEXTIO.write(TX_OUT, string'("Total[]"));
		STD.TEXTIO.writeline(results, TX_OUT);
		ASSERT (FALSE) REPORT
			"Success! Simulation for annotation completed"
			SEVERITY FAILURE;
	END PROCESS;
END testbench_arch;

CONFIGURATION serial_cfg OF test IS
	FOR testbench_arch
	END FOR;
END serial_cfg;