代码搜索：State Machine

找到约 10,000 项符合「State Machine」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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srd state2.srd

f "noname"; #file 0 f "c:\eda\synplicity\fpga_81\lib\altera\altera.v"; #file 1 f "c:\eda\synplicity\fpga_81\lib\altera\stratix.v"; #file 2 f "c:\eda\synplicity\fpga_81\lib\altera\altera_mf.v"; #fil
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srm state2.srm

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srr state2.srr

#Program: Synplify Pro 8.1 #OS: Windows_NT $ Start of Compile #Fri Dec 16 18:27:34 2005 Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May 3 2005 Copyright (C) 1994-2005, Synp
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vif state2.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2005 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file stat
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sxr state2.sxr

BeginView state2 NoName Inst: CS[1] CS_1__Z stratix_lcell_ff Inst: CS[0] CS_0__Z stratix_lcell_ff Inst: o2_x o2_x_cZ stratix_lcell Inst: err_0_x err_0_x_cZ stratix_lcell Inst: err_x
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fse state2.fse

fsm_encoding {4280281} sequential fsm_state_encoding {4280281} IDLE {00} fsm_state_encoding {4280281} S1 {01} fsm_state_encoding {4280281} S2 {10} fsm_state_encoding {4280281} ERROR {11}
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tlg state2.tlg

Selecting top level module state2 @N:"C:\prj\Example-6-1\FSM\state2\state2.v":7:7:7:12|Synthesizing module state2 @N: CL201 :"C:\prj\Example-6-1\FSM\state2\state2.v":28:0:28:5|Trying to extract st
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prf state2.prf

# # Logical Preferences generated for Lucent by Synplify 8.1.0, Build 532R. # # Period Constraints FREQUENCY PORT "clk" 364.2 MHz; # Output Constraints # Input Constraints BLOCK ASYNCPATHS;
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vqm state2.vqm

// // Written by Synplify // Synplify 8.1.0, Build 539R. // Fri Dec 16 18:27:37 2005 // // Source file index table: // Object locations will have the form : // file 0 "noname" // f
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xrf state2.xrf

vendor_name = Synplicity source_file = 0, noname, synplify source_file = 1, c:\eda\synplicity\fpga_81\lib\altera\altera.v, synplify source_file = 2, c:\eda\synplicity\fpga_81\lib\altera\stratix.v,
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