state2.fse

来自「《设计与验证Verilog HDL》光盘内容」· FSE 代码 · 共 13 行

fsm_encoding {4280281} sequential

fsm_state_encoding {4280281} IDLE {00}

fsm_state_encoding {4280281} S1 {01}

fsm_state_encoding {4280281} S2 {10}

fsm_state_encoding {4280281} ERROR {11}

fsm_registers {4280281} {CS[1]}  {CS[0]}