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module ALARM_STATE_MACHINE(CLK, HRS, MINS, ALARM, HRS_OUT, MINS_OUT); input CLK, HRS, MINS, ALARM; output HRS_OUT, MINS_OUT; wire CLK, HRS, MINS, ALARM; reg HRS_OUT, MINS_OUT; reg [1:0] STATE, NE

module TIME_STATE_MACHINE(CLK, HRS, MINS, SET_TIME, HRS_OUT, MINS_OUT, SECS_OUT); input wire CLK, HRS, MINS, SET_TIME; output reg SECS_OUT, HRS_OUT, MINS_OUT; reg [1:0] STATE, NEXTSTATE; parameter

Flow report for state_machine Fri Oct 20 16:36:40 2006 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice

module state_machine(clk,rst,c,en); input clk,rst; output[7:0] c; reg[7:0] c; output[7:0] en; parameter state0=3'b000, state1=3'b001, state2=3'b010, state3=3'b011, state4=

Timing Analyzer report for state_machine Fri Oct 20 16:36:40 2006 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Lega

Assembler report for state_machine Fri Oct 20 16:36:38 2006 Version 5.1 Build 176 10/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Noti

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-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Analysis & Synthesis Status : Successful - Fri Oct 20 16:36:32 2006 Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version Revision Name : state_machine Top-level Entity Name : state_machine