alarm_state_machine.v

基于verilog的时钟定时器的硬件实现

module ALARM_STATE_MACHINE(CLK, HRS, MINS, ALARM, HRS_OUT, MINS_OUT);
input CLK, HRS, MINS, ALARM;
output HRS_OUT, MINS_OUT;
wire CLK, HRS, MINS, ALARM;
reg HRS_OUT, MINS_OUT;
reg [1:0] STATE, NEXTSTATE;
parameter IDLE= 2'b00, SET_HOURS= 2'b01, SET_MINUTES= 2'b10;

always@(posedge CLK)
  case(STATE)
     IDLE:
        begin
           HRS_OUT<= 0; MINS_OUT<= 0;
           if(ALARM==1 & HRS==1 & MINS==0)
              NEXTSTATE<= SET_HOURS;
           else if(ALARM==1 & HRS==0 & MINS==1)
              NEXTSTATE<= SET_MINUTES;
        end
     SET_HOURS:
        begin
           HRS_OUT<= 1; MINS_OUT<= 0; 
           if(ALARM==1 & HRS==1 & MINS==0)
              NEXTSTATE<= STATE;
           else
              NEXTSTATE<= IDLE;
        end
    SET_MINUTES:
        begin
           HRS_OUT<= 0; MINS_OUT<= 1;
           if(ALARM==1 & HRS==0 & MINS==1)
              NEXTSTATE<= STATE;
           else
              NEXTSTATE<= IDLE;
        end
    default:
        begin
           HRS_OUT<= 0; MINS_OUT<= 0;
           NEXTSTATE<= IDLE;
        end
  endcase
  
  
always@(posedge CLK)
  STATE<= NEXTSTATE;
  
endmodule