time_state_machine.v

基于verilog的时钟定时器的硬件实现

module TIME_STATE_MACHINE(CLK, HRS, MINS, SET_TIME, HRS_OUT, MINS_OUT, SECS_OUT);
input wire CLK, HRS, MINS, SET_TIME;
output reg SECS_OUT, HRS_OUT, MINS_OUT;
reg [1:0] STATE, NEXTSTATE;
parameter COUNT_TIME= 2'b00, 
          SET_MINUTES= 2'b01,
          SET_HOURS= 2'b10;

always@ (posedge CLK)
case (STATE)
  COUNT_TIME:
        begin
            SECS_OUT<= 1; MINS_OUT<= 0; HRS_OUT<= 0;
          if(SET_TIME==1 & HRS==0 & MINS==1)
             NEXTSTATE <= SET_MINUTES;
          else if(SET_TIME==1 & HRS==1 & MINS==0)
             NEXTSTATE <= SET_HOURS;
          else NEXTSTATE <= STATE;
        end
  SET_MINUTES:
        begin
            SECS_OUT<= 0; MINS_OUT<= 1; HRS_OUT<= 0;
          if(SET_TIME==1 & HRS==0 & MINS==1)
             NEXTSTATE <= STATE;
          else 
             NEXTSTATE <= COUNT_TIME;
        end
  SET_HOURS:
        begin
            SECS_OUT<= 0; MINS_OUT<= 0; HRS_OUT<= 1;
          if(SET_TIME==1 & HRS==1 & MINS==0)
             NEXTSTATE <= STATE;
          else 
             NEXTSTATE <= COUNT_TIME;
        end
  default:
         begin
             SECS_OUT<= 1; MINS_OUT<= 0; HRS_OUT<= 0;
         NEXTSTATE <= COUNT_TIME;
         end
endcase

always@(posedge CLK)
     STATE<= NEXTSTATE;
     
endmodule