代码搜索结果

State Machine - |state_control|current_state Name current_state.done_msg current_state.timer current_state.set_clock current_state.lamp_test current_state.idle current_state.idle 0 0 0 0 0 curr

State Machine - |uart_top|uart_core:U_Core|state Name state.uart_end_recv state.uart_recv state.uart_end_send state.uart_send state.uart_load state.uart_idle state.uart_idle 0 0 0 0 0 0 state.u

State Machine - |traffic|state Name state.A state.G state.B state.C state.D state.E state.F state.IDLE state.IDLE 0 0 0 0 0 0 0 0 state.F 0 0 0 0 0 0 1 1 state.E 0 0 0 0 0 1 0 1 state.D 0 0

State Machine - |wash|state:inst5|c_st Name c_st.st4 c_st.st3 c_st.st2 c_st.st1 c_st.st0 c_st.st0 0 0 0 0 0 c_st.st1 0 0 0 1 1 c_st.st2 0 0 1 0 1 c_st.st3 0 1 0 0 1 c_st.st4 1 0 0 0 1

State Machine - |fpga2pc|STATE Name STATE.IDLE STATE.WRITE_2 STATE.WRITE_1 STATE.IDLE 0 0 0 STATE.WRITE_2 1 1 0 STATE.WRITE_1 1 0 1

State Machine - |pc2fpga|STATE Name STATE.IDLE STATE.READ_2 STATE.READ_1 STATE.IDLE 0 0 0 STATE.READ_2 1 1 0 STATE.READ_1 1 0 1

State Machine - |sram_test|STATE Name STATE.WRITE_1 STATE.WRITE_2 STATE.READ_1 STATE.IDLE STATE.READ_2 STATE.IDLE 0 0 0 0 0 STATE.READ_1 0 0 1 1 0 STATE.WRITE_2 0 1 0 1 0 STATE.READ_2 0 0 0

State Machine - |ad0820|sinA:inst7|state_key Name state_key.k3 state_key.k2 state_key.k1 state_key.k0 state_key.k0 0 0 0 0 state_key.k1 0 0 1 1 state_key.k2 0 1 0 1 state_key.k3 1 0 0 1

State Machine - |rs|RSDecoder:inst1|rsdec:rsdec|MainControl:controller|state1 Name state1.st1_14 state1.st1_1 state1.st1_2 state1.st1_3 state1.st1_4 state1.st1_5 state1.st1_6 state1.st1_7 state1.st

Verilog HDL: Synchronous State Machine This is a Verilog example that shows the implementation of a state machine. The first CASE statement defines the outputs that are dependent on the value of