state_machine.vhd.bak

这个是Xilinx编程的源码

--------------------------------------
--  entity       = state_machine           --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
--------------------------------------


-- main control unit for the sorting process

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.Numeric_STD.all;


entity state_machine is
 port ( clk : in std_logic;
        clear : in std_logic;
        reset : in std_logic;
        nrdy : in std_logic; -- enable active low
        lt : in std_logic; -- less than active
        eq : in std_logic;
        srd : out std_logic_vector(2 downto 0); -- address to read register file
        swr : out std_logic_vector(2 downto 0); -- address to write register file
        inp : out std_logic; -- select input for register file
        enwr : out std_logic; -- enable write register file
        nack : out std_logic -- done when low
      );
end;  

architecture struct of state_machine is

type state_type is (state1,state2,state3,state4,state5,state6,state7); -- a total of 7 states to sort 5 numbers

type state_register_type is record
	state : state_type;
end record;

signal r, r_in: state_register_type; -- state register

begin

control: process(r,nrdy,lt,eq) -- sorting

variable v : state_register_type;
variable vsrd : std_logic_vector(2 downto 0); 
variable vswr : std_logic_vector(2 downto 0);
variable venwr, vnack, vinp : std_logic;

begin

v.state := r.state;
vinp := '0';
venwr := '0';
vnack := '1';
vsrd := "000";
vswr := "000";


case v.state is

	when state1 =>  -- firs state
		if (nrdy = '0' and lt = '0') then
			v.state := state2;
		elsif (nrdy = '0') then
			v.state := state7;
		end if;
		vnack := '1';
		
	when state2 => 
		if (lt = '0') then
			v.state := state3;
		else
			vinp := '1';
			v.state := state7;
		end if;
		vsrd := "001";
		venwr := '1';
		vnack := '1';	
	when state3 =>
		if (lt = '0' ) then 
			v.state := state4;
		else
			vinp := '1';
			v.state := state7;
		end if;
		vswr := "001";
		vsrd := "010";
		venwr := '1';
		vnack := '1';	
	when state4 => 
		if (lt = '0') then 
			v.state := state5;
		else
			vinp := '1';
			v.state := state7;
		end if;
		vswr := "010";
		vsrd := "011";
		venwr := '1';
		vnack := '1';	
	when state5 =>
		if (lt = '0') then 
			v.state := state6;
		else
			vinp := '1';
			v.state := state7;
		end if;
		vswr := "011";
		vsrd := "100";
		venwr := '1';
		vnack := '1';
	when state6 =>
		v.state := state7;
		vswr := "100";
		venwr := '1';
		vinp := '1';
		vnack := '1';
	when state7 =>
		if (nrdy = '1') then
			v.state := state1;
		end if;
		vnack := '0';
	when others => null;
	
	end case;
	
	swr <= vswr;
	srd <= vsrd;
	enwr <= venwr;
	inp <= vinp;
	nack <= vnack;
	r_in.state <= v.state;
		
end process control;


-- sequential part

regs: process (clk,clear)

begin

if (clear = '1') then
	r.state <= state1;
elsif rising_edge(clk) then
	if (reset = '1') then
		r.state <= state1;
	else
		r.state <= r_in.state;
	end if;
end if;

end process regs;

end;