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example_en_24bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_24bit_s.sch
-- Aug 14, 2003 16:14
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a
example_en_24bit_s.v
/* Verilog Model Created from SCS Schematic example_en_24bit_s.sch
Aug 14, 2003 16:14 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_en_24bit_s.vh
/* Verilog Header Created from SCS Schematic example_en_24bit_s.sch
Aug 14, 2003 16:14 */
module example_en_24bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
out
gate_clock.pcf
SCHEMATIC START ;
SCHEMATIC END ;
map.pcf
SCHEMATIC START ;
SCHEMATIC END ;
gate_clock2.pcf
SCHEMATIC START ;
SCHEMATIC END ;
map.pcf
SCHEMATIC START ;
SCHEMATIC END ;
gate_clock.pcf
SCHEMATIC START ;
SCHEMATIC END ;
map.pcf
SCHEMATIC START ;
SCHEMATIC END ;
gate_clock2.pcf
SCHEMATIC START ;
SCHEMATIC END ;