📄 keyscan.map.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Apr 23 21:19:47 2009 " "Info: Processing started: Thu Apr 23 21:19:47 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off keyscan -c keyscan " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off keyscan -c keyscan" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keys_decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keys_decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keys_decoder-one " "Info: Found design unit 1: keys_decoder-one" { } { { "keys_decoder.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_decoder.vhd" 12 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keys_decoder " "Info: Found entity 1: keys_decoder" { } { { "keys_decoder.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_decoder.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_block.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_block.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_block-one " "Info: Found design unit 1: clk_block-one" { } { { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 13 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_block " "Info: Found entity 1: clk_block" { } { { "clk_block.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/clk_block.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pre_key.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pre_key.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pre_key " "Info: Found entity 1: pre_key" { } { { "pre_key.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/pre_key.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_dounce4.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_dounce4.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 key_dounce4 " "Info: Found entity 1: key_dounce4" { } { { "key_dounce4.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/key_dounce4.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keys_display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file keys_display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 keys_display-one " "Info: Found design unit 1: keys_display-one" { } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 12 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 keys_display " "Info: Found entity 1: keys_display" { } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 6 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keyscan.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file keyscan.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 keyscan " "Info: Found entity 1: keyscan" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "keyscan " "Info: Elaborating entity \"keyscan\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keys_display keys_display:inst2 " "Info: Elaborating entity \"keys_display\" for hierarchy \"keys_display:inst2\"" { } { { "keyscan.bdf" "inst2" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 8 400 576 104 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "segout keys_display.vhd(9) " "Warning (10541): VHDL Signal Declaration warning at keys_display.vhd(9): used implicit default value for signal \"segout\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 9 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "seg keys_display.vhd(14) " "Warning (10036): Verilog HDL or VHDL warning at keys_display.vhd(14): object \"seg\" assigned a value but never read" { } { { "keys_display.vhd" "" { Text "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keys_display.vhd" 14 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "keys_decoder keys_decoder:inst3 " "Info: Elaborating entity \"keys_decoder\" for hierarchy \"keys_decoder:inst3\"" { } { { "keyscan.bdf" "inst3" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 168 400 584 296 "inst3" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_block clk_block:inst " "Info: Elaborating entity \"clk_block\" for hierarchy \"clk_block:inst\"" { } { { "keyscan.bdf" "inst" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 16 128 272 112 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_dounce4 key_dounce4:inst1 " "Info: Elaborating entity \"key_dounce4\" for hierarchy \"key_dounce4:inst1\"" { } { { "keyscan.bdf" "inst1" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 200 80 264 296 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pre_key key_dounce4:inst1\|pre_key:inst " "Info: Elaborating entity \"pre_key\" for hierarchy \"key_dounce4:inst1\|pre_key:inst\"" { } { { "key_dounce4.bdf" "inst" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/key_dounce4.bdf" { { 8 144 280 104 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[6\] GND " "Warning (13410): Pin \"SEGOUT\[6\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[5\] GND " "Warning (13410): Pin \"SEGOUT\[5\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[4\] GND " "Warning (13410): Pin \"SEGOUT\[4\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[3\] GND " "Warning (13410): Pin \"SEGOUT\[3\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[2\] GND " "Warning (13410): Pin \"SEGOUT\[2\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[1\] GND " "Warning (13410): Pin \"SEGOUT\[1\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "SEGOUT\[0\] GND " "Warning (13410): Pin \"SEGOUT\[0\]\" is stuck at GND" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 400 416 592 416 "SEGOUT\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 0} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "Warning (15610): No output dependent on input pin \"KEY\[3\]\"" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[2\] " "Warning (15610): No output dependent on input pin \"KEY\[2\]\"" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[1\] " "Warning (15610): No output dependent on input pin \"KEY\[1\]\"" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[0\] " "Warning (15610): No output dependent on input pin \"KEY\[0\]\"" { } { { "keyscan.bdf" "" { Schematic "F:/电子信息工程/4我的专业课程/可编程逻辑器件实验/4矩阵键盘控制接口实验/keyscan.bdf" { { 344 56 224 360 "KEY\[3..0\]" "" } } } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0 0} } { } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "27 " "Info: Implemented 27 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "10 " "Info: Implemented 10 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Peak virtual memory: 174 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Apr 23 21:19:51 2009 " "Info: Processing ended: Thu Apr 23 21:19:51 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
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