uart.prf

一个UART的FPGA core

SCHEMATIC START ;
# map:  version ispLever_v51_Prod_Build (38) -- WARNING: Map write only section -- Fri Jul 07 14:17:00 2006

SYSCONFIG INBUF=ON CONFIG_SECURE=OFF ;
LOCATE COMP "data_0" SITE "3" ;
LOCATE COMP "inter" SITE "108" ;
LOCATE COMP "clk" SITE "58" ;
LOCATE COMP "we_en1" SITE "95" ;
LOCATE COMP "baud_clk" SITE "100" ;
LOCATE COMP "txd_0" SITE "34" ;
LOCATE COMP "rxd_0" SITE "33" ;
LOCATE COMP "oe_n" SITE "24" ;
LOCATE COMP "we_n" SITE "25" ;
LOCATE COMP "cs_n" SITE "28" ;
LOCATE COMP "data_7" SITE "12" ;
LOCATE COMP "data_6" SITE "9" ;
LOCATE COMP "data_5" SITE "8" ;
LOCATE COMP "data_4" SITE "7" ;
LOCATE COMP "data_3" SITE "6" ;
LOCATE COMP "data_2" SITE "5" ;
LOCATE COMP "data_1" SITE "4" ;
LOCATE COMP "addr_4" SITE "20" ;
LOCATE COMP "addr_3" SITE "17" ;
LOCATE COMP "addr_2" SITE "15" ;
LOCATE COMP "addr_1" SITE "14" ;
LOCATE COMP "addr_0" SITE "13" ;
LOCATE COMP "rst" SITE "76" ;
LOCATE COMP "clk_in" SITE "55" ;
FREQUENCY PORT "clk" 50.000000 MHz ;
SCHEMATIC END ;
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
USE PRIMARY NET "clk_c" ;
USE PRIMARY NET "baud_clk_c" ;
USE PRIMARY NET "clk_in_c" ;
USE PRIMARY NET "baud_clk1_c" ;