代码搜索结果

ftce_mxilinx_cnt60 NULL J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf sub00/vhpl00 ftce_mxilinx_cnt60 schematic J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf sub00/vhpl01 cb4ce_mxilinx_cnt60 NULL

@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\mico8.vhd":10:7:10:11|Synthesizing work.mico8.schematic @W: CD638 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\mico8.vhd":37:10:37:12|Signa

电源电路 *SPICE Netlist generated by Advanced Sim server on 2010-5-26 8:32:48 *Schematic Netlist: C1 0 OUT 1uF L1 0 OUT 1mH R1A OUT IN {1K * 0.5} R1B IN IN {1K -(1K * 0.5 )} VIN IN 0 DC 0 SIN(0 1

Common-Emmiter Amplifier *SPICE Netlist generated by Advanced Sim server on 11/06/2002 4:37:38 PM *Schematic Netlist: C1 IN B 0.01uF C2 C OUT 0.01uF C3 E 0 0.01uF Q1 C B E 2N2222A R1 VCC B 18

Common-Emmiter Amplifier *SPICE Netlist generated by Advanced Sim server on 11/06/2002 4:37:38 PM *Schematic Netlist: C1 IN B 0.01uF C2 C OUT 0.01uF C3 E 0 0.01uF Q1 C B E 2N2222A R1 VCC B 18

电源电路 *SPICE Netlist generated by Advanced Sim server on 2010-5-26 8:32:48 *Schematic Netlist: C1 0 OUT 1uF L1 0 OUT 1mH R1A OUT IN {1K * 0.5} R1B IN IN {1K -(1K * 0.5 )} VIN IN 0 DC 0 SIN(0 1

/* Verilog model created from schematic protect.sch -- Aug 16, 2006 14:36 */ module protect( P, PSO, Q1, Q2, Q3, R1A, R1B, R2, R3, RESET, S ); input P; output PSO, Q1, Q2, Q3; input R1A, R1B,

Common-Emmiter Amplifier *SPICE Netlist generated by Advanced Sim server on 2006-12-2 0:53:47 *Schematic Netlist: C1 IN B 0.01uF C2 C OUT 0.01uF C3 E 0 0.01uF Q1 C B E 2N2222A R1 VCC B 18k R

Common-Emmiter Amplifier *SPICE Netlist generated by Advanced Sim server on 2006-12-6 15:25:11 *Schematic Netlist: C1 IN B 0.01uF C2 C OUT 0.01uF C3 E 0 0.01uF Q1 C B E 2N2222A R1 VCC B 18k

Push-Pull Amplifier *SPICE Netlist generated by Advanced Sim server on 11/06/2002 4:15:41 PM *Schematic Netlist: C1 IN A 1.26uF Q1 VCC B1 OUT 2N2219A Q2 VSS B2 OUT 2N2905A R1 VCC B1 16k R2 B1