mico8.tlg

Lattice 超精简8位软核CPU--Mico8

@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\mico8.vhd":10:7:10:11|Synthesizing work.mico8.schematic 
@W: CD638 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\mico8.vhd":37:10:37:12|Signal gnd is undriven 
@W: CD638 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\mico8.vhd":38:10:38:12|Signal vcc is undriven 
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\SysCntrl.vhd":56:7:56:15|Synthesizing work.sys_cntrl.behaviour 
Post processing for work.sys_cntrl.behaviour
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\My_pll.vhd":14:7:14:12|Synthesizing work.my_pll.structure 
@W: CD280 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\My_pll.vhd":34:14:34:16|Unbound component VLO mapped to black box
@W: CD280 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\My_pll.vhd":37:14:37:20|Unbound component EHXPLLD mapped to black box
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\My_pll.vhd":37:14:37:20|Synthesizing work.ehxplld.syn_black_box 
Post processing for work.ehxplld.syn_black_box
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\My_pll.vhd":34:14:34:16|Synthesizing work.vlo.syn_black_box 
Post processing for work.vlo.syn_black_box
Post processing for work.my_pll.structure
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\ProgPRom.vhd":14:7:14:14|Synthesizing work.progprom.structure 
@W: CD280 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\ProgPRom.vhd":30:14:30:16|Unbound component VHI mapped to black box
@W: CD280 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\ProgPRom.vhd":36:14:36:19|Unbound component DP16KB mapped to black box
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\ProgPRom.vhd":36:14:36:19|Synthesizing work.dp16kb.syn_black_box 
Post processing for work.dp16kb.syn_black_box
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\ProgPRom.vhd":30:14:30:16|Synthesizing work.vhi.syn_black_box 
Post processing for work.vhi.syn_black_box
Post processing for work.progprom.structure
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\SEROUT_M8.vhd":54:7:54:15|Synthesizing work.serout_m8.behave 
Post processing for work.serout_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":54:7:54:12|Synthesizing work.pwm_m8.behave 
@N: CD364 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":117:3:117:8|Removed redundant assignment
Post processing for work.pwm_m8.behave
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(8) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(9) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(10) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(11) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(12) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(13) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(14) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to duty(15) assign '0', register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 8 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 9 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 10 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 11 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 12 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 13 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 14 of duty(15 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\pwm_m8.vhd":79:1:79:2|All reachable assignments to bit 15 of duty(15 downto 0) assign 0, register removed by optimization
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\led_m8.vhd":54:7:54:12|Synthesizing work.led_m8.behave 
Post processing for work.led_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\tx_uart_M8.vhd":63:7:63:16|Synthesizing work.tx_uart_m8.behave 
@N: CD233 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\tx_uart_M8.vhd":90:19:90:20|Using sequential encoding for type txstate_type
Post processing for work.tx_uart_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\lcd_m8.vhd":57:7:57:12|Synthesizing work.lcd_m8.behave 
Post processing for work.lcd_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\seg7_m8.vhd":60:7:60:13|Synthesizing work.seg7_m8.behave 
Post processing for work.seg7_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":78:7:78:18|Synthesizing work.int_handl_m8.behave 
@N: CD233 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":111:13:111:14|Using sequential encoding for type state
@W: CD604 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":231:3:231:16|OTHERS clause is not synthesized 
Post processing for work.int_handl_m8.behave
@W: CL169 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":194:1:194:2|Pruning Register INT_Set  
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to INT_REG(4) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to INT_REG(5) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to INT_REG(6) assign '0', register removed by optimization
@W: CL111 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to INT_REG(7) assign '0', register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to bit 4 of INT_REG(7 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to bit 5 of INT_REG(7 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to bit 6 of INT_REG(7 downto 0) assign 0, register removed by optimization
@W: CL208 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\int_handl_m8.vhd":122:1:122:2|All reachable assignments to bit 7 of INT_REG(7 downto 0) assign 0, register removed by optimization
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\DIP8_M8.vhd":57:7:57:13|Synthesizing work.dip8_m8.behave 
@N: CD233 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\DIP8_M8.vhd":69:13:69:14|Using sequential encoding for type state
@W: CD604 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\DIP8_M8.vhd":109:3:109:16|OTHERS clause is not synthesized 
Post processing for work.dip8_m8.behave
@N: CD630 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\RX_uart_M8.vhd":59:7:59:16|Synthesizing work.rx_uart_m8.behave 
@N: CD233 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\RX_uart_M8.vhd":79:21:79:22|Using sequential encoding for type uartstate_type
@W: CD604 :"C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\RX_uart_M8.vhd":114:2:114:15|OTHERS clause is not synthesized 
Post processing for work.rx_uart_m8.behave