protect.vf

这是一个开发gal16v8器件的详细源代码

/* Verilog model created from schematic protect.sch -- Aug 16, 2006 14:36 */

module protect( P, PSO, Q1, Q2, Q3, R1A, R1B, R2, R3, RESET, S );
 input P;
output PSO, Q1, Q2, Q3;
 input R1A, R1B, R2, R3;
output RESET;
 input S;
wire N_24;
wire N_25;
wire N_26;
wire N_27;
wire N_14;
wire N_17;
wire N_18;
wire N_19;
wire N_20;
wire N_21;
wire N_22;
wire N_4;
wire N_5;
wire N_9;
wire N_10;
wire N_11;
wire N_1;
wire N_2;

not I26 ( N_25, N_26 );
not I19 ( N_4, N_22 );
not I20 ( N_5, N_21 );
not I22 ( N_14, N_19 );
not I24 ( N_24, N_17 );
buf I6 ( N_17, P );
buf I7 ( N_18, R1A );
buf I8 ( N_22, R3 );
buf I9 ( N_21, R2 );
buf I10 ( N_20, S );
buf I11 ( N_19, R1B );
buf I13 ( Q2, N_10 );
buf I12 ( Q3, N_9 );
buf I14 ( Q1, N_11 );
buf I15 ( PSO, N_27 );
buf I16 ( RESET, N_25 );
3rs I5 ( .Q1(N_11), .Q2(N_10), .Q3(N_9), .R1(N_1), .R2(N_5), .R3(N_4), .S(N_20) );
and I3 ( N_26, N_27, N_24 );
and I1 ( N_1, N_14, N_18 );
and I2 ( N_2, N_9, N_10 );
and I4 ( N_27, N_2, N_11 );

endmodule // protect