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ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: G:\单片机小组\DS1302时钟+DS18B20+无线遥控应用程序\DS1302.DSN Doc. no.: Revision: Author: Created: 0

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: G:\单片机小组\DS1302时钟+DS18B20+无线遥控应用程序\DS1302.DSN Doc. no.: Revision: Author: Created: 0

config dummy_root_design; design newpro001_lib.dummy_root_design:sch_1; liblist newpro001_lib, new_library; viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional; stoplist chips; endco

config dummy_root_design; design newpro001_lib.dummy_root_design:sch_1; liblist newpro001_lib, new_library; viewlist chips, pic_1, picopt_1, sch_1, schematic, entity, functional; stoplist chips; endco

# Schematic : View HDL Functional Model clock.vhf clock.cmd_log # XST (Creating Lso File) : clock.lso # xst flow : RunXST clock.syr clock.prj clock.sprj clock.ana clock.stx clock.cmd_log

`timescale 1ps / 1ps /* Verilog Header Created from SCS Schematic example_en_32bit_a.sch Aug 14, 2003 11:13 */ module example_en_32bit_a( clear_in , clk_in, enable_in, count_out ); input

`timescale 1ps / 1ps /* Verilog Header Created from SCS Schematic example_16bit_load.sch Aug 15, 2003 11:19 */ module example_16bit_load( clear_in , clk_in, data, enable_in, load_in, coun

/* Verilog Header Created from SCS Schematic example_en_32bit_s.sch Aug 14, 2003 16:38 */ module example_en_32bit_s( clear_in , clk_in, enable_in, count_out ); input clear_in, clk_in; out

/* Verilog Header Created from SCS Schematic example_en_16bit_s.sch Aug 14, 2003 12:15 */ module example_en_16bit_s( clear_in , clk_in, enable_in, count_out ); input clear_in, clk_in; out

`timescale 1ps / 1ps /* Verilog Header Created from SCS Schematic example_en_4bit.sch Aug 13, 2003 12:30 */ module example_en_4bit( clear_in , clk_in, enable_in, count_out ); input clear