example_en_32bit_s.vh

VHDL examples for counter design, use QuickLogic eclips

/* Verilog Header Created from SCS Schematic example_en_32bit_s.sch 
   Aug 14, 2003 16:38 */


module example_en_32bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
 output [31:0] count_out;
input enable_in;