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ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\a-51新书\book\ex8\ex8-2\ex8-2.DSN Doc. no.: Revision: Author: Created: 13/12/06 Mo

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\a-51新书\book\ex8\ex8-7\ex8-7.DSN Doc. no.: Revision: Author: Created: 04/01/15 Mo

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\a-51新书\book\ex8\ex8-6\ex8-6.DSN Doc. no.: Revision: Author: Created: 13/12/06 Mo

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\a-51新书\book\ex8\ex8-1\ex8-1.DSN Doc. no.: Revision: Author: Created: 13/12/06 Mo

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\a-51新书\book\ex8\ex8-5\ex8-5.DSN Doc. no.: Revision: Author: Created: 06/08/06 Mo

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: C:\Documents and Settings\Administrator\桌面\教学支持包成品\工程文件\十八、DS18B20实验\DS18B20.DSN Doc. no.: Revision:

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: F:\单片机\做好的项目\项目（下载）.C\Max7221动态显示\Max7221.DSN Doc. no.: Revision: Author: Created: 0

-- Vhdl model created from schematic samkmorsy.sch - Fri Jun 18 19:45:46 2004 LIBRARY ieee; LIBRARY UNISIM; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE UNISIM.Vcomponents.ALL;

-- Vhdl model created from schematic batmouse.sch - Mon Jun 21 22:49:06 2004 LIBRARY ieee; LIBRARY UNISIM; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE UNISIM.Vcomponents.ALL;

// Verilog test fixture created from schematic top.sch - Thu Jan 10 13:03:21 2008 `timescale 1ns / 1ps module top_top_sch_tb(); // Inputs reg clk; reg rst; // Output wire clkbp