testall.v

来自「SONY公司出品的黑白CCD（44万像素）ICX229的驱动信号产生程序」· Verilog 代码 · 共 79 行

// Verilog test fixture created from schematic top.sch - Thu Jan 10 13:03:21 2008

`timescale 1ns / 1ps

module top_top_sch_tb();

// Inputs
   reg clk;
   reg rst;

// Output
   wire clkbp;
   wire v1;
   wire v1h;
   wire v2;
   wire v3;
   wire v3h;
   wire v4;
	wire sub;
   wire h1;
   wire h2;
   wire r;
   
	wire shp;
   wire shd;
   wire adcck;
   wire clpob;
   wire pblk;
	wire clpdm;

   wire reset;
   wire sload;
	wire sclk;
   wire sdata;

// Bidirs

// Instantiate the UUT
   top UUT (
	   .clk(clk), 
		.rst(rst), 
		.clkbp(clkbp),

		.v1(v1), 
		.v1h(v1h), 
		.v2(v2), 
		.v3(v3), 
		.v3h(v3h), 
		.v4(v4), 
		.h1(h1), 
		.h2(h2), 
		.r(r), 
		.sub(sub),

		.clpdm(clpdm), 
		.shp(shp), 
		.shd(shd), 
		.adcck(adcck), 
		.clpob(clpob), 
		.pblk(pblk), 
 
		.reset(reset), 
		.sload(sload),
		.sclk(sclk),
		.sdata(sdata)
   );
always #10 clk=~clk;
	initial begin
		// Initialize Inputs
	   clk = 0;
		rst = 1;
		#10 rst=0;
		#1010 rst=1;

		// Wait 100 ns for global reset to finish
		#100000;
	end
endmodule