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Schematic 的代码
schcvt.ini
[General]
Default Input=Protel 99SE/DXP
Default Output=PADS Logic
[Protel 99SE/DXP -> PADS Logic - General]
Config File=C:\Program Files\Mentor Graphics\Translators\Schematic\protel2pl.cnv
[Prote
example_en_4bit.vhd
-- VHDL Model Created from SCS Schematic example_en_4bit.sch
-- Aug 13, 2003 12:31
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.all;
example_24bit_load.v
/* Verilog Model Created from SCS Schematic example_24bit_load.sch
Aug 15, 2003 11:51 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_8bit_load.v
/* Verilog Model Created from SCS Schematic example_8bit_load.sch
Aug 15, 2003 10:41 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_8bit_load.vhd
-- VHDL Model Created from SCS Schematic example_8bit_load.sch
-- Aug 15, 2003 10:41
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_16bit_load.v
/* Verilog Model Created from SCS Schematic example_16bit_load.sch
Aug 15, 2003 11:19 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_32bit_load.v
/* Verilog Model Created from SCS Schematic example_32bit_load.sch
Aug 15, 2003 13:22 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOG
example_4bit_load.v
/* Verilog Model Created from SCS Schematic example_4bit_load.sch
Aug 15, 2003 10:23 */
/* Automatically generated by hvveri version 9.5 Release Build2 */
`timescale 1ns/1ns
`define LOGI
example_4bit_load.vhd
-- VHDL Model Created from SCS Schematic example_4bit_load.sch
-- Aug 15, 2003 10:23
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.al
example_en_32bit_s.vhd
-- VHDL Model Created from SCS Schematic example_en_32bit_s.sch
-- Aug 14, 2003 16:39
-- Automatically generated by vdvhdl version 9.5 Release Build2
library IEEE;
use IEEE.std_logic_1164.a