example_4bit_load.v

VHDL examples for counter design, use QuickLogic eclips

/* Verilog Model Created from SCS Schematic example_4bit_load.sch 
   Aug 15, 2003 10:23 */

/* Automatically generated by hvveri version 9.5 Release Build2 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_4bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in, clk_in;
 output [3:0] count_out;
 input [3:0] data;
input enable_in, load_in;
parameter syn_macro = 1;
wire [3:0] data_in;
wire [3:0] count;
wire [3:0] data_in_reg;
wire [3:0] count_reg;
wire load_reg;
wire enable_reg;
wire load;
wire enable;
wire clear;
wire clk;

counter_4bit_load I12 ( .clear(clear), .clk(clk),
                     .data_in({ data_in_reg[3:0] }), .enable(enable_reg),
                     .load(load_reg), .Qa_c(count[3]), .Qb_c(count[2]),
                     .Qc_c(count[1]), .Qd_c(count[0]) );
rg4_25um I1 ( .CLK(clk), .D({ data_in[3:0] }), .Q({ data_in_reg[3:0] }) );
rg4_25um I2 ( .CLK(clk), .D({ count[3:0] }), .Q({ count_reg[3:0] }) );
dff_2 I3 ( .CLK(clk), .D1(enable), .D2(load), .Q1(enable_reg), .Q2(load_reg) );
opad4_25um I4 ( .A({ count_reg[3:0] }), .P({ count_out[3:0] }) );
ipad4_25um I5 ( .P({ data[3:0] }), .Q({ data_in[3:0] }) );
inpad_25um I6 ( .P(load_in), .Q(load) );
inpad_25um I7 ( .P(enable_in), .Q(enable) );
ckpad_25um I8 ( .P(clear_in), .Q(clear) );
ckpad_25um I9 ( .P(clk_in), .Q(clk) );

endmodule // example_4bit_load


`ifdef counter_4bit_load
`else
`define counter_4bit_load
module counter_4bit_load( clear , clk, data_in, enable, load, Qa_c, Qb_c, Qc_c,
                          Qd_c );
input clear, clk;
 input [3:0] data_in;
input enable, load;
output Qa_c, Qb_c, Qc_c, Qd_c;
parameter syn_macro = 1;
wire Qb_r;
wire Qa_r;
wire Qb_a;
wire Qa_a;
wire Qc_a;
wire Qc_r;
wire enable_buf;
wire Qd_r;
wire Qd_a;
wire load_N;
supply0 gnd;
supply1 vcc;

super_logic I17 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
               .B1(data_in[2]), .B2(gnd), .C1(gnd), .C2(gnd), .D1(Qb_r),
               .D2(gnd), .E1(vcc), .E2(Qb_r), .F1(Qc_r), .F2(gnd), .F3(Qd_r),
               .F4(gnd), .F5(vcc), .F6(gnd), .MP(gnd), .MS(gnd),
               .NP(enable_buf), .NS(gnd), .OP(gnd), .OS(load_N), .OZ(Qb_a),
               .PP(vcc), .PS(Qb_a), .Q2Z(Qb_c), .QC(clk), .QR(clear), .QS(gnd),
               .QZ(Qb_r) );
super_logic I16 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
               .B1(data_in[3]), .B2(gnd), .C1(gnd), .C2(gnd), .D1(Qa_r),
               .D2(gnd), .E1(vcc), .E2(Qa_r), .F1(Qb_r), .F2(gnd), .F3(Qc_r),
               .F4(gnd), .F5(Qd_r), .F6(gnd), .MP(gnd), .MS(gnd),
               .NP(enable_buf), .NS(gnd), .OP(gnd), .OS(load_N), .OZ(Qa_a),
               .PP(vcc), .PS(Qa_a), .Q2Z(Qa_c), .QC(clk), .QR(clear), .QS(gnd),
               .QZ(Qa_r) );
super_logic I18 ( .A1(enable), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
               .AZ(enable_buf), .B1(data_in[1]), .B2(gnd), .C1(gnd), .C2(gnd),
               .D1(Qc_r), .D2(gnd), .E1(vcc), .E2(Qc_r), .F1(Qd_c), .F2(gnd),
               .F3(vcc), .F4(gnd), .F5(vcc), .F6(gnd), .MP(gnd), .MS(gnd),
               .NP(enable_buf), .NS(gnd), .OP(gnd), .OS(load_N), .OZ(Qc_a),
               .PP(vcc), .PS(Qc_a), .Q2Z(Qc_c), .QC(clk), .QR(clear), .QS(gnd),
               .QZ(Qc_r) );
super_logic I3 ( .A1(vcc), .A2(load), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .AZ(load_N), .B1(data_in[0]), .B2(gnd), .C1(gnd), .C2(gnd),
              .D1(Qd_c), .D2(gnd), .E1(vcc), .E2(Qd_c), .F1(vcc), .F2(gnd),
              .F3(vcc), .F4(gnd), .F5(vcc), .F6(gnd), .MP(gnd), .MS(gnd),
              .NP(enable_buf), .NS(gnd), .OP(vcc), .OS(gnd), .OZ(Qd_a),
              .PP(vcc), .PS(Qd_a), .Q2Z(Qd_c), .QC(clk), .QR(clear), .QS(gnd),
              .QZ(Qd_r) );

endmodule // counter_4bit_load

`endif

`ifdef rg4_25um
`else
`define rg4_25um
module rg4_25um( CLK , D, Q );
input CLK;
 input [3:0] D;
 output [3:0] Q;
parameter syn_macro = 1;

dff_2 I3 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I4 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg4_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK, D1, D2;
output Q1, Q2;
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1) );

endmodule // dff_2

`endif

`ifdef opad4_25um
`else
`define opad4_25um
module opad4_25um( A , P );
 input [3:0] A;
 output [3:0] P;
parameter syn_macro = 1;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );

endmodule // opad4_25um

`endif

`ifdef ipad4_25um
`else
`define ipad4_25um
module ipad4_25um( P , Q );
 input [3:0] P;
 output [3:0] Q;
parameter syn_macro = 1;

inpad_25um I1 ( .P(P[3]), .Q(Q[3]) );
inpad_25um I2 ( .P(P[2]), .Q(Q[2]) );
inpad_25um I3 ( .P(P[1]), .Q(Q[1]) );
inpad_25um I4 ( .P(P[0]), .Q(Q[0]) );

endmodule // ipad4_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
 wire EQMUX_Z, OQMUX_Z; 
 reg EQZ, OQQ, IQQ; 
 assign #1 EQMUX_Z = ESEL ? IE : EQZ; 
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ; 
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz; 
 assign #1 IZ = IP; 

  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      EQZ <= #1 1'b0;
    else if (EQE)
      EQZ <= #1 IE; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      IQQ <= #1 1'b0; 
    else if (IQE) 
      IQQ <= #1 IP; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR) 
      OQQ <= #1 1'b0; 
    else 
      OQQ <= #1 OQI; 

endmodule // eio_cell

`endif

`ifdef ckcell_25um
`else
`define ckcell_25um
module ckcell_25um( IP , IC );
output IC;
input IP;
parameter syn_macro = 1;
parameter ql_frag = 1;
 assign #1 IC = IP;

endmodule // ckcell_25um

`endif

`ifdef super_cell
`else
`define super_cell
module super_cell( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                   F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC, QR,
                   QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_frag = 1;
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z, FFMUX_Z, CLKMUX_Z; 
 wire MZ; 
 reg QZ, Q2Z; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS; 
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2) : (B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS; 
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2) : (D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS; 
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ; 
 assign #1 FFMUX_Z = PP ? PS : NZ; 
`ifdef synthesis 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else 
        #1 QZ = OZ; 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
     else 
        #1 Q2Z = FFMUX_Z; 
`else 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 QZ = OZ; 
  always @ (QR or QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 Q2Z = FFMUX_Z; 
  always @ (QR or QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
`endif 

endmodule // super_cell

`endif