example_24bit_load.v

VHDL examples for counter design, use QuickLogic eclips

/* Verilog Model Created from SCS Schematic example_24bit_load.sch 
   Aug 15, 2003 11:51 */

/* Automatically generated by hvveri version 9.5 Release Build2 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_24bit_load( clear_in , clk_in, data, enable_in, load_in, count_out );
input clear_in, clk_in;
 output [23:0] count_out;
 input [23:0] data;
input enable_in, load_in;
parameter syn_macro = 1;
wire [23:0] count_reg;
wire [23:0] data_in;
wire [23:0] data_reg;
wire [23:0] count;
wire load_reg;
wire enable_reg;
wire clear;
wire load;
wire enable;
wire clk;

counter_24bit_load I14 ( .clear(clear), .clk(clk), .count({ count[23:0] }),
                      .data_in({ data_reg[23:0] }), .enable(enable_reg),
                      .load(load_reg) );
outpad_25um \outpad_25um[23]  ( .A(count_reg[23]), .P(count_out[23]) );
outpad_25um \outpad_25um[22]  ( .A(count_reg[22]), .P(count_out[22]) );
outpad_25um \outpad_25um[21]  ( .A(count_reg[21]), .P(count_out[21]) );
outpad_25um \outpad_25um[20]  ( .A(count_reg[20]), .P(count_out[20]) );
outpad_25um \outpad_25um[19]  ( .A(count_reg[19]), .P(count_out[19]) );
outpad_25um \outpad_25um[18]  ( .A(count_reg[18]), .P(count_out[18]) );
outpad_25um \outpad_25um[17]  ( .A(count_reg[17]), .P(count_out[17]) );
outpad_25um \outpad_25um[16]  ( .A(count_reg[16]), .P(count_out[16]) );
outpad_25um \outpad_25um[15]  ( .A(count_reg[15]), .P(count_out[15]) );
outpad_25um \outpad_25um[14]  ( .A(count_reg[14]), .P(count_out[14]) );
outpad_25um \outpad_25um[13]  ( .A(count_reg[13]), .P(count_out[13]) );
outpad_25um \outpad_25um[12]  ( .A(count_reg[12]), .P(count_out[12]) );
outpad_25um \outpad_25um[11]  ( .A(count_reg[11]), .P(count_out[11]) );
outpad_25um \outpad_25um[10]  ( .A(count_reg[10]), .P(count_out[10]) );
outpad_25um \outpad_25um[9]  ( .A(count_reg[9]), .P(count_out[9]) );
outpad_25um \outpad_25um[8]  ( .A(count_reg[8]), .P(count_out[8]) );
outpad_25um \outpad_25um[7]  ( .A(count_reg[7]), .P(count_out[7]) );
outpad_25um \outpad_25um[6]  ( .A(count_reg[6]), .P(count_out[6]) );
outpad_25um \outpad_25um[5]  ( .A(count_reg[5]), .P(count_out[5]) );
outpad_25um \outpad_25um[4]  ( .A(count_reg[4]), .P(count_out[4]) );
outpad_25um \outpad_25um[3]  ( .A(count_reg[3]), .P(count_out[3]) );
outpad_25um \outpad_25um[2]  ( .A(count_reg[2]), .P(count_out[2]) );
outpad_25um \outpad_25um[1]  ( .A(count_reg[1]), .P(count_out[1]) );
outpad_25um \outpad_25um[0]  ( .A(count_reg[0]), .P(count_out[0]) );
rg8 I12 ( .CLK(clk), .D({ data_in[23:16] }), .Q({ data_reg[23:16] }) );
rg8 I13 ( .CLK(clk), .D({ count[23:16] }), .Q({ count_reg[23:16] }) );
rg16_25um I1 ( .CLK(clk), .D({ data_in[15:0] }), .Q({ data_reg[15:0] }) );
rg16_25um I2 ( .CLK(clk), .D({ count[15:0] }), .Q({ count_reg[15:0] }) );
dff_2 I3 ( .CLK(clk), .D1(enable), .D2(load), .Q1(enable_reg), .Q2(load_reg) );
inpad_25um \inpad_25um[23]  ( .P(data[23]), .Q(data_in[23]) );
inpad_25um \inpad_25um[22]  ( .P(data[22]), .Q(data_in[22]) );
inpad_25um \inpad_25um[21]  ( .P(data[21]), .Q(data_in[21]) );
inpad_25um \inpad_25um[20]  ( .P(data[20]), .Q(data_in[20]) );
inpad_25um \inpad_25um[19]  ( .P(data[19]), .Q(data_in[19]) );
inpad_25um \inpad_25um[18]  ( .P(data[18]), .Q(data_in[18]) );
inpad_25um \inpad_25um[17]  ( .P(data[17]), .Q(data_in[17]) );
inpad_25um \inpad_25um[16]  ( .P(data[16]), .Q(data_in[16]) );
inpad_25um \inpad_25um[15]  ( .P(data[15]), .Q(data_in[15]) );
inpad_25um \inpad_25um[14]  ( .P(data[14]), .Q(data_in[14]) );
inpad_25um \inpad_25um[13]  ( .P(data[13]), .Q(data_in[13]) );
inpad_25um \inpad_25um[12]  ( .P(data[12]), .Q(data_in[12]) );
inpad_25um \inpad_25um[11]  ( .P(data[11]), .Q(data_in[11]) );
inpad_25um \inpad_25um[10]  ( .P(data[10]), .Q(data_in[10]) );
inpad_25um \inpad_25um[9]  ( .P(data[9]), .Q(data_in[9]) );
inpad_25um \inpad_25um[8]  ( .P(data[8]), .Q(data_in[8]) );
inpad_25um \inpad_25um[7]  ( .P(data[7]), .Q(data_in[7]) );
inpad_25um \inpad_25um[6]  ( .P(data[6]), .Q(data_in[6]) );
inpad_25um \inpad_25um[5]  ( .P(data[5]), .Q(data_in[5]) );
inpad_25um \inpad_25um[4]  ( .P(data[4]), .Q(data_in[4]) );
inpad_25um \inpad_25um[3]  ( .P(data[3]), .Q(data_in[3]) );
inpad_25um \inpad_25um[2]  ( .P(data[2]), .Q(data_in[2]) );
inpad_25um \inpad_25um[1]  ( .P(data[1]), .Q(data_in[1]) );
inpad_25um \inpad_25um[0]  ( .P(data[0]), .Q(data_in[0]) );
inpad_25um I6 ( .P(load_in), .Q(load) );
inpad_25um I7 ( .P(enable_in), .Q(enable) );
ckpad_25um I8 ( .P(clear_in), .Q(clear) );
ckpad_25um I9 ( .P(clk_in), .Q(clk) );

endmodule // example_24bit_load


`ifdef counter_24bit_load
`else
`define counter_24bit_load
module counter_24bit_load( clear , clk, data_in, enable, load, count, enable_1,
                           enable_2, enable_3, enable_4, enable_5, enable_6 );
input clear, clk;
 output [23:0] count;
 input [23:0] data_in;
input enable;
output enable_1, enable_2, enable_3, enable_4, enable_5, enable_6;
input load;
parameter syn_macro = 1;

counter_16bit_load I8 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
                     .data_in({ data_in[15:0] }), .enable(enable),
                     .enable_1(enable_1), .enable_2(enable_2),
                     .enable_3(enable_3), .enable_4(enable_4), .load(load) );
counter_8bit_iii_load I9 ( .clear(clear), .clk(clk), .count({ count[23:16] }),
                        .data_in({ data_in[23:16] }), .enable(enable),
                        .enable_1(enable_1), .enable_2(enable_2),
                        .enable_3(enable_3), .enable_4(enable_4),
                        .enable_5_r(enable_5), .enable_6_r(enable_6),
                        .load(load) );

endmodule // counter_24bit_load

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef rg8
`else
`define rg8
module rg8( CLK , D, Q );
input CLK;
 input [7:0] D;
 output [7:0] Q;
parameter syn_macro = 1;

dff QL7 ( .CLK(CLK), .D(D[0]), .Q(Q[0]) );
dff QL6 ( .CLK(CLK), .D(D[1]), .Q(Q[1]) );
dff QL5 ( .CLK(CLK), .D(D[2]), .Q(Q[2]) );
dff QL4 ( .CLK(CLK), .D(D[3]), .Q(Q[3]) );
dff QL3 ( .CLK(CLK), .D(D[4]), .Q(Q[4]) );
dff QL2 ( .CLK(CLK), .D(D[5]), .Q(Q[5]) );
dff QL1 ( .CLK(CLK), .D(D[6]), .Q(Q[6]) );
dff QL8 ( .CLK(CLK), .D(D[7]), .Q(Q[7]) );

endmodule // rg8

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK;
 input [15:0] D;
 output [15:0] Q;
parameter syn_macro = 1;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK, D1, D2;
output Q1, Q2;
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1) );

endmodule // dff_2

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef counter_16bit_load
`else
`define counter_16bit_load
module counter_16bit_load( clear , clk, data_in, enable, load, count, enable_1,
                           enable_2, enable_3, enable_4 );
input clear, clk;
 output [15:0] count;
 input [15:0] data_in;
input enable;
output enable_1, enable_2, enable_3, enable_4;
input load;
parameter syn_macro = 1;

counter_8bit_ii_load I10 ( .clear(clear), .clk(clk), .count({ count[15:8] }),
                        .data_in({ data_in[15:8] }), .enable(enable),
                        .enable_1(enable_1), .enable_2(enable_2),
                        .enable_3(enable_3), .enable_4(enable_4),
                        .load(load) );
counter_8bit_i_load I11 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
                       .data_in({ data_in[7:0] }), .enable(enable),
                       .enable_2(enable_2), .fo_enable(enable_1),
                       .load(load) );

endmodule // counter_16bit_load

`endif

`ifdef counter_8bit_iii_load
`else
`define counter_8bit_iii_load
module counter_8bit_iii_load( clear , clk, data_in, enable, enable_1, enable_2,
                              enable_3, enable_4, load, count, enable_5_r,
                              enable_6_r );
input clear, clk;
 output [7:0] count;
 input [7:0] data_in;
input enable, enable_1, enable_2, enable_3, enable_4;
output enable_5_r, enable_6_r;
input load;
parameter syn_macro = 1;
wire enable_in2_a;
wire load_buf1_a;
wire enable_in1_a;
wire load_buf2_a;
supply1 vcc;
supply0 gnd;

counter_4bit_load I18 ( .clear(clear), .clk(clk), .data_in({ data_in[3:0] }),
                     .enable(enable_in1_a), .load(load_buf1_a),
                     .Qa_c(count[3]), .Qb_c(count[2]), .Qc_c(count[1]),
                     .Qd_c(count[0]) );
counter_4bit_load I19 ( .clear(clear), .clk(clk), .data_in({ data_in[7:4] }),
                     .enable(enable_in2_a), .load(load_buf2_a),
                     .Qa_c(count[7]), .Qb_c(count[6]), .Qc_c(count[5]),
                     .Qd_c(count[4]) );
super_logic I12 ( .A1(count[7]), .A2(gnd), .A3(count[6]), .A4(gnd), .A5(count[5]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[4]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(load), .F2(gnd), .F3(vcc),
               .F4(gnd), .F5(vcc), .F6(gnd), .FZ(load_buf1_a), .MP(gnd),
               .MS(gnd), .NP(gnd), .NS(gnd), .OP(vcc), .OS(gnd), .PP(gnd),
               .PS(gnd), .QC(clk), .QR(clear), .QS(gnd), .QZ(enable_6_r) );
super_logic I16 ( .A1(enable), .A2(gnd), .A3(enable_1), .A4(gnd), .A5(enable_2),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(enable_4),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(enable_in1_a), .F2(gnd),
               .F3(enable_5_r), .F4(gnd), .F5(vcc), .F6(gnd),
               .FZ(enable_in2_a), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd),
               .OP(enable_3), .OS(gnd), .OZ(enable_in1_a), .PP(gnd), .PS(gnd),
               .QC(clk), .QR(clear), .QS(gnd) );
super_logic I15 ( .A1(count[3]), .A2(gnd), .A3(count[2]), .A4(gnd), .A5(count[1]),
               .A6(gnd), .B1(gnd), .B2(gnd), .C1(vcc), .C2(gnd), .D1(count[0]),
               .D2(gnd), .E1(vcc), .E2(gnd), .F1(load), .F2(gnd), .F3(vcc),
               .F4(gnd), .F5(vcc), .F6(gnd), .FZ(load_buf2_a), .MP(gnd),
               .MS(gnd), .NP(gnd), .NS(gnd), .OP(vcc), .OS(gnd), .PP(gnd),
               .PS(gnd), .QC(clk), .QR(clear), .QS(gnd), .QZ(enable_5_r) );

endmodule // counter_8bit_iii_load

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
 wire EQMUX_Z, OQMUX_Z; 
 reg EQZ, OQQ, IQQ; 
 assign #1 EQMUX_Z = ESEL ? IE : EQZ; 
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ; 
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz; 
 assign #1 IZ = IP; 

  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      EQZ <= #1 1'b0;
    else if (EQE)
      EQZ <= #1 IE; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR)
      IQQ <= #1 1'b0; 
    else if (IQE) 
      IQQ <= #1 IP; 
  always @ (posedge IQC or posedge IQR) 
    if (IQR) 
      OQQ <= #1 1'b0; 
    else 
      OQQ <= #1 OQI; 

endmodule // eio_cell

`endif

`ifdef dff
`else
`define dff
module dff( CLK , D, Q );
input CLK, D;
output Q;
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;
supply0 GND;
wire N_1;