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Schematic 的代码
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: C:\Documents and Settings\tiger\桌面\Keil+Proteus-10-1\2个8051串行通信\2_8051.DSN
Doc. no.:
Revision:
cardbus_5632.v
/* Verilog Model Created from SCS Schematic cardbus_5632.sch
Apr 08, 2004 05:30 */
/* Automatically generated by hvveri version 9.5.3 Release Build1 */
`timescale 1ns/1ns
`define LOGIC
cardbus_5632.vhd
-- VHDL Model Created from SCS Schematic cardbus_5632.sch
-- Apr 07, 2004 22:23
-- Automatically generated by vdvhdl version 9.5.3 Release Build1
library IEEE;
use IEEE.std_logic_1164.all;
claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR
claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR
claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR
lisa1.sdf
ISIS SCHEMATIC DESCRIPTION FORMAT 6.1
=====================================
Design: F:\单片机\单片机项目-li\汉字显示\123.DSN
Doc. no.:
Revision:
Author:
Created: 07/12/02
Modified
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
stopwatch.vf
// Verilog model created from schematic stopwatch.sch - Thu Dec 05 17:54:29 2002
`timescale 1ns / 1ps
module stopwatch(clk, reset, strstop, onesout, tensout, tenthsout);
input clk;
input
claadd8s.v
/* Verilog Model Created from SCS Schematic claadd8s.sch
Mar 22, 1996 23:48 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR