cardbus_5632.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

-- VHDL Model Created from SCS Schematic cardbus_5632.sch 
-- Apr 07, 2004 22:23 

-- Automatically generated by vdvhdl version 9.5.3 Release Build1 

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity AFIFOFLG is
      Port (     clk : In    STD_LOGIC;
             holdoff : In    STD_LOGIC;
                 one : In    STD_LOGIC;
               reset : In    STD_LOGIC;
                  rw : In    STD_LOGIC;
                 set : In    STD_LOGIC;
                 two : In    STD_LOGIC;
                zero : In    STD_LOGIC;
             almost_on : Out   STD_LOGIC;
             flag_on : Out   STD_LOGIC );
end AFIFOFLG;


architecture SCHEMATIC of AFIFOFLG is

   signal     N_10 : STD_LOGIC;
   signal      N_8 : STD_LOGIC;
   signal      N_9 : STD_LOGIC;
   signal  zero_r1 : STD_LOGIC;
   signal      N_1 : STD_LOGIC;
   signal      N_3 : STD_LOGIC;
   signal nzeronone : STD_LOGIC;
   signal nzeronone_r1 : STD_LOGIC;
   signal      N_4 : STD_LOGIC;
   signal      N_7 : STD_LOGIC;
   signal almost_on_DUMMY : STD_LOGIC;
   signal flag_on_DUMMY : STD_LOGIC;

   component OR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND3I3
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I2
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component MUX2X2
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   S : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component AND2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFFPC
      Port (     CLK : In    STD_LOGIC;
                 CLR : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                 PRE : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component DFF
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

begin


   almost_on <= almost_on_DUMMY;
   flag_on <= flag_on_DUMMY;
   I26 : OR2I0
      Port Map ( A=>N_9, B=>one, Q=>N_8 );
   I23 : AND3I3
      Port Map ( A=>zero_r1, B=>zero, C=>holdoff, Q=>N_3 );
   I15 : AND2I2
      Port Map ( A=>zero, B=>one, Q=>nzeronone );
   I16 : MUX2X2
      Port Map ( A=>N_10, B=>N_3, S=>flag_on_DUMMY, Q=>N_1 );
   I17 : MUX2X2
      Port Map ( A=>N_8, B=>N_7, S=>almost_on_DUMMY, Q=>N_4 );
   I19 : AND2I0
      Port Map ( A=>rw, B=>almost_on_DUMMY, Q=>N_10 );
   I24 : AND2I0
      Port Map ( A=>nzeronone, B=>nzeronone_r1, Q=>N_7 );
   I20 : AND2I0
      Port Map ( A=>rw, B=>two, Q=>N_9 );
   I21 : DFFPC
      Port Map ( CLK=>clk, CLR=>reset, D=>N_1, PRE=>set,
                 Q=>flag_on_DUMMY );
   I22 : DFFPC
      Port Map ( CLK=>clk, CLR=>reset, D=>N_4, PRE=>set,
                 Q=>almost_on_DUMMY );
   I25 : DFF
      Port Map ( CLK=>clk, D=>nzeronone, Q=>nzeronone_r1 );
   I13 : DFF
      Port Map ( CLK=>clk, D=>zero, Q=>zero_r1 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity ECOMP5 is
      Port (       A : In    STD_LOGIC_VECTOR (4 downto 0);
                   B : In    STD_LOGIC_VECTOR (4 downto 0);
                  EQ : Out   STD_LOGIC );
end ECOMP5;


architecture SCHEMATIC of ECOMP5 is

   signal      N_5 : STD_LOGIC;
   signal      N_1 : STD_LOGIC;
   signal      N_4 : STD_LOGIC;
   signal EQ_DUMMY : STD_LOGIC;

   component AND3I1
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   C : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component XOR2I0
      Port (       A : In    STD_LOGIC;
                   B : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
   end component;

   component ECOMPA
      Port (       A : In    STD_LOGIC_VECTOR  (0 to 1);
                   B : In    STD_LOGIC_VECTOR  (0 to 1);
                 EQ2 : Out   STD_LOGIC );
   end component;

begin


   EQ <= EQ_DUMMY;
   I_11 : AND3I1
      Port Map ( A=>N_1, B=>N_4, C=>N_5, Q=>EQ_DUMMY );
   I_12 : XOR2I0
      Port Map ( A=>A(4), B=>B(4), Q=>N_5 );
   I_9 : ECOMPA
      Port Map ( A(0)=>A(2), A(1)=>A(3), B(0)=>B(2), B(1)=>B(3),
                 EQ2=>N_4 );
   I_10 : ECOMPA
      Port Map ( A(0)=>A(0), A(1)=>A(1), B(0)=>B(0), B(1)=>B(1),
                 EQ2=>N_1 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity DFFPA is
      Port (     CLK : In    STD_LOGIC;
                   D : In    STD_LOGIC;
                   S : In    STD_LOGIC;
                   Q : Out   STD_LOGIC );
end DFFPA;


architecture SCHEMATIC of DFFPA is

	attribute ql_gate   : integer;
	attribute ql_gate of SCHEMATIC : architecture is QL_LOGIC;
   signal      N_1 : STD_LOGIC;
   signal      N_2 : STD_LOGIC;
	constant 		VCC : STD_LOGIC := '1';
   signal      N_3 : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
   signal Q_DUMMY : STD_LOGIC;

   component FRAG_F
      Port (      F1 : In    STD_LOGIC;
                  F2 : In    STD_LOGIC;
                  F3 : In    STD_LOGIC;
                  F4 : In    STD_LOGIC;
                  F5 : In    STD_LOGIC;
                  F6 : In    STD_LOGIC;
                  FZ : Out   STD_LOGIC );
   end component;

   component FRAG_A
      Port (      A1 : In    STD_LOGIC;
                  A2 : In    STD_LOGIC;
                  A3 : In    STD_LOGIC;
                  A4 : In    STD_LOGIC;
                  A5 : In    STD_LOGIC;
                  A6 : In    STD_LOGIC;
                  AZ : Out   STD_LOGIC );
   end component;

   component FRAG_Q
      Port (      QC : In    STD_LOGIC;
                  QD : In    STD_LOGIC;
                  QR : In    STD_LOGIC;
                  QS : In    STD_LOGIC;
                  QZ : Out   STD_LOGIC );
   end component;

   component FRAG_M
      Port (      B1 : In    STD_LOGIC;
                  B2 : In    STD_LOGIC;
                  C1 : In    STD_LOGIC;
                  C2 : In    STD_LOGIC;
                  D1 : In    STD_LOGIC;
                  D2 : In    STD_LOGIC;
                  E1 : In    STD_LOGIC;
                  E2 : In    STD_LOGIC;
                \NS\ : In    STD_LOGIC;
                  OS : In    STD_LOGIC;
                  NZ : Out   STD_LOGIC;
                  OZ : Out   STD_LOGIC );
   end component;

begin


   Q <= Q_DUMMY;
   I_3 : FRAG_F
      Port Map ( F1=>VCC, F2=>GND, F3=>VCC, F4=>GND, F5=>VCC, F6=>GND,
                 FZ=>N_1 );
   I_2 : FRAG_A
      Port Map ( A1=>VCC, A2=>GND, A3=>VCC, A4=>GND, A5=>VCC, A6=>GND,
                 AZ=>N_2 );
   I_1 : FRAG_Q
      Port Map ( QC=>CLK, QD=>N_3, QR=>GND, QS=>S, QZ=>Q_DUMMY );
   QL1 : FRAG_M
      Port Map ( B1=>VCC, B2=>GND, C1=>VCC, C2=>GND, D1=>VCC, D2=>GND,
                 E1=>D, E2=>GND, \NS\=>N_1, OS=>N_2, NZ=>open, OZ=>N_3 );

end SCHEMATIC;

library IEEE;
use IEEE.std_logic_1164.all;
use work.QL_PACKAGE.all;

entity F32A32_25UM is
      Port (     din : In    STD_LOGIC_VECTOR (31 downto 0);
                 pop : In    STD_LOGIC;
                push : In    STD_LOGIC;
                rclk : In    STD_LOGIC;
                rrst : In    STD_LOGIC;
                wclk : In    STD_LOGIC;
                wrst : In    STD_LOGIC;
             almostempty : Out   STD_LOGIC;
             almostfull : Out   STD_LOGIC;
                dout : Out   STD_LOGIC_VECTOR (31 downto 0);
               empty : Out   STD_LOGIC;
                full : Out   STD_LOGIC );
end F32A32_25UM;


architecture SCHEMATIC of F32A32_25UM is

   signal   Raddr2 : STD_LOGIC_VECTOR (4 downto 0);
   signal   Waddr2 : STD_LOGIC_VECTOR (4 downto 0);
   signal   Waddr3 : STD_LOGIC_VECTOR (4 downto 0);
   signal   Waddr0 : STD_LOGIC_VECTOR (4 downto 0);
   signal   Raddr1 : STD_LOGIC_VECTOR (4 downto 0);
   signal    plus2 : STD_LOGIC;
   signal    plus1 : STD_LOGIC;
   signal     zero : STD_LOGIC;
   signal   minus1 : STD_LOGIC;
   signal   minus2 : STD_LOGIC;
	constant 		GND : STD_LOGIC := '0';
   signal      N_2 : STD_LOGIC;
   signal      N_3 : STD_LOGIC;
   signal      N_4 : STD_LOGIC;
   signal      N_9 : STD_LOGIC;
   signal     N_10 : STD_LOGIC;
   signal     N_11 : STD_LOGIC;
   signal almostempty_DUMMY : STD_LOGIC;
   signal almostfull_DUMMY : STD_LOGIC;
   signal dout_DUMMY : STD_LOGIC_VECTOR  (31 downto 0);
   signal empty_DUMMY : STD_LOGIC;
   signal full_DUMMY : STD_LOGIC;

   component R128X32_25UM
      Port (      ra : In    STD_LOGIC_VECTOR  (6 downto 0);
                rclk : In    STD_LOGIC;
                  re : In    STD_LOGIC;
                  wa : In    STD_LOGIC_VECTOR  (6 downto 0);
                wclk : In    STD_LOGIC;
                  wd : In    STD_LOGIC_VECTOR  (31 downto 0);
                  we : In    STD_LOGIC;
                  rd : Out   STD_LOGIC_VECTOR  (31 downto 0) );
   end component;

   component AFIFOFLG
      Port (     clk : In    STD_LOGIC;
             holdoff : In    STD_LOGIC;
                 one : In    STD_LOGIC;
               reset : In    STD_LOGIC;
                  rw : In    STD_LOGIC;
                 set : In    STD_LOGIC;
                 two : In    STD_LOGIC;
                zero : In    STD_LOGIC;