cardbus_5632.v

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

/* Verilog Model Created from SCS Schematic cardbus_5632.sch 
   Apr 08, 2004 05:30 */

/* Automatically generated by hvveri version 9.5.3 Release Build1 */

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 
`include "f64x4.v" 
`include "cis_decode.v" 
`include "cfgtaddr_cardbus.v" 
`include "D:/pasic/spde/data/ql5632-33/PCI32_25UM/pci32_25um.v" 
`include "cardbus_wrapper.v" 
`include "dmaregrd.v" 
`include "fifocont.v" 
`include "initflgs.v" 
`include "dmacntrl.v" 
`include "r128x32_25um.v" 
`include "gcnte5_0.v" 
`include "rgec5_1r.v" 
`include "rgec5_2.v" 
`include "gcnte5_2.v" 
`include "gcnte5_3.v" 

module cardbus_5632( CLK , GNTN, IDSEL, ir_n, lclk, or_n, pad_BAM, pad_bvd,
                     pad_CBLOCK_n, pad_CIS_data, pad_clk_resume, pad_gwake,
                     pad_intr, pad_PWM, pad_ready, pad_wp, pae_n, paf_n, RSTN,
                     INTAN, ld, led, mrs, oe, pad_CAUDIO, pad_CINT_n,
                     pad_CIS_ADR, pad_clk_stopped, pad_CSTSCHG, pad_locked,
                     pad_owner_access, ren, REQN, SERRN, wen, AD, CBEN,
                     DEVSELN, FRAMEN, IRDYN, lad, pad_CCLKRUN_n, PAR, PERRN,
                     STOPN, TRDYN );
 inout [31:0] AD;
 inout [3:0] CBEN;
input CLK;
inout DEVSELN, FRAMEN;
input GNTN, IDSEL;
output INTAN;
input ir_n;
inout IRDYN;
 inout [31:0] lad;
input lclk;
output ld;
 output [7:0] led;
output mrs, oe;
input or_n, pad_BAM;
 input [2:1] pad_bvd;
output pad_CAUDIO;
input pad_CBLOCK_n;
inout pad_CCLKRUN_n;
output pad_CINT_n;
 output [9:2] pad_CIS_ADR;
 input [31:0] pad_CIS_data;
input pad_clk_resume;
output pad_clk_stopped, pad_CSTSCHG;
input pad_gwake, pad_intr;
output pad_locked, pad_owner_access;
input pad_PWM, pad_ready, pad_wp, pae_n, paf_n;
inout PAR, PERRN;
output ren, REQN;
input RSTN;
output SERRN;
inout STOPN, TRDYN;
output wen;
wire [31:0] Mst_WrData;
wire [31:0] Mst_WrData_FIFO;
wire [3:0] Usr_CBE;
wire [7:2] Cfg_CacheLineSize;
wire [31:0] Cfg_RdData;
wire [9:0] ADR;
wire [7:0] Cfg_LatCnt;
wire [3:0] Mst_BE;
wire [31:0] Mst_RdAd;
wire [31:0] Mst_WrAd;
wire [3:0] PCI_Cmd;
wire [31:0] WrBuff_in;
wire [31:0] RdBuff_out;
wire [31:0] mem_RdData;
wire [31:0] Usr_RdData;
wire [31:0] cstschg_regs;
wire [31:0] RdBuff_mux;
wire [31:0] WrD;
wire [3:0] Mst_BE_FIFO;
wire [31:0] Mst_WrData_Reg;
wire [7:0] ledout;
wire [7:0] mxledoi;
wire [7:0] mxledo;
wire [31:0] Usr_RdDataIn;
supply0 GND_bit;
wire [31:0] CIS_data;
wire [15:0] Cfg_CmdReg;
wire [2:1] bvd_ps;
wire [31:0] Usr_Addr_WrData;
wire locked;
wire owner_access;
wire clk_stopped;
wire CINT_n;
wire CSTSCHG;
wire CAUDIO;
wire CCLKRUN_n_in;
wire CCLKRUN_n_out;
wire CCLKRUN_n_oe;
wire CBLOCK_n;
wire PWM_in;
wire BAM_in;
wire wp_ps;
wire ready_ps;
wire gwake_ps;
wire intr_ps;
wire clk_resume;
wire Usr_Stop;
wire Usr_Last_Cycle_D1;
wire N_18;
wire N_19;
wire N_20;
wire s1s0;
wire s0en;
wire s1en;
wire DMAWrEn;
wire DMARdEn;
wire ledcntrl;
wire BEfifo;
wire BEFIFO_fulln;
wire N_21;
wire N_22;
wire N_23;
wire N_24;
wire N_25;
wire WrBuff_almost_full;
wire re_dly;
wire RdBuff_fullN;
wire RdBuff_almost_empty;
wire we_int;
wire N_26;
wire N_27;
wire N_28;
wire N_29;
wire N_30;
wire N_31;
wire N_32;
wire Prog_Stop;
wire CIS_sel;
wire cstschg_rdy;
wire Mem_Rdy;
wire RdData_MUX_sel;
wire CardBus_BAR;
wire Usr_Read;
wire PCI_FRAME_D1;
supply1 VCC;
wire ldn;
wire we_out;
wire fifo_oe_n;
wire re_out;
wire fpga_oe;
wire WrBuff_fullN;
wire local_clock;
wire Mst_WrData_Valid;
wire DMA_Error;
wire Usr_MstRdAd_Sel;
wire local_reset;
wire Usr_MstWrAd_Sel;
wire Mst_One_Read;
wire RdBuff_empty_sync;
wire Mst_Xfer_D1;
wire Mst_Two_Reads;
wire loc_sync_reset;
wire WrBuff_emptyN;
wire LocalEn;
wire WrBuff_almost_empty;
wire Mst_WrBurst_Done;
wire Mst_LatCntEn;
wire Mst_RdBurst_Done;
wire Mst_Rd_Term_Sel;
supply0 GND;
wire Mst_RdData_Valid;
wire Cfg_PERR_Det;
wire Cfg_MstPERR_Det;
wire Cfg_SERR_Sig;
wire irn_in;
wire pafn_in;
wire paen_in;
wire orn_in;
wire RdBuff_empty;
wire RdBuff_full;
wire WrBuff_empty;
wire WrBuff_full;
wire Mst_Tabort_Det;
wire Mst_TTO_Det;
wire Usr_Rdy;
wire Usr_Write;
wire Cfg_Write;
wire Cfg_Stop;
wire Mst_Data_Sel;
wire Usr_Adr_Valid;
wire Usr_Adr_Inc;
wire Usr_Select;
wire Usr_RdDecode;
wire Usr_WrDecode;
wire Mst_WrData_Rdy;
wire PCI_reset;
wire Mst_BE_Sel;
wire Mst_Burst_Req;
wire BEFIFO_pop;
wire BEFIFO_emptyn;
wire PCI_clock;
wire MstSC;

f64x4 I251 ( .clk(PCI_clock), .din({ Usr_Addr_WrData[3:0] }),
          .dout({ Mst_BE_FIFO[3:0] }), .emptyn(BEFIFO_emptyn),
          .fulln(BEFIFO_fulln), .pop(BEFIFO_pop), .push(BEfifo),
          .rst(PCI_reset) );
cis_decode I250 ( .addr_phase(Usr_Adr_Valid), .BAR_match(CardBus_BAR),
               .CIS_Hit(CIS_sel), .clk(PCI_clock),
               .last_cycle(Usr_Last_Cycle_D1), .reset(PCI_reset),
               .user_addr({ Usr_Addr_WrData[9:4] }) );
cfgtaddr_cardbus I249 ( .Addr_Hit(Usr_Select), .BAR5_Hit(CardBus_BAR),
                     .CacheLineSizeReg({ Cfg_CacheLineSize[7:2] }),
                     .CBE({ Usr_CBE[3:0] }), .Cfg_Write(Cfg_Write),
                     .CfgData({ Cfg_RdData[31:0] }),
                     .CmdReg({ Cfg_CmdReg[15:0] }), .IncrAddr(Usr_Adr_Inc),
                     .LatTimerReg({ Cfg_LatCnt[7:0] }),
                     .LoadAddr(Usr_Adr_Valid),
                     .MstPERR_Det(Cfg_MstPERR_Det), .MstSC(MstSC),
                     .PCI_clock(PCI_clock), .PCI_reset(PCI_reset),
                     .PERR_Det(Cfg_PERR_Det), .SERR_Sig(Cfg_SERR_Sig),
                     .Tabort_Det(Mst_Tabort_Det), .TTO_Det(Mst_TTO_Det),
                     .Usr_RdCmd(Usr_RdDecode), .Usr_Stop(Cfg_Stop),
                     .Usr_WrCmd(Usr_WrDecode), .UsrAddr({ ADR[9:0] }),
                     .WrData({ Usr_Addr_WrData[31:0] }) );
pci32_25um I248 ( .AD({ AD[31:0] }), .CBEN({ CBEN[3:0] }),
               .Cfg_CacheLineSize({ Cfg_CacheLineSize[7:2] }),
               .Cfg_CmdReg3(Cfg_CmdReg[3]), .Cfg_CmdReg4(Cfg_CmdReg[4]),
               .Cfg_CmdReg6(Cfg_CmdReg[6]), .Cfg_CmdReg8(Cfg_CmdReg[8]),
               .Cfg_LatCnt({ Cfg_LatCnt[7:0] }),
               .Cfg_MstPERR_Det(Cfg_MstPERR_Det),
               .Cfg_PERR_Det(Cfg_PERR_Det),
               .Cfg_RdData({ Cfg_RdData[31:0] }),
               .Cfg_SERR_Sig(Cfg_SERR_Sig), .Cfg_Write(Cfg_Write), .CLK(CLK),
               .DEVSELN(DEVSELN), .Flush_FIFO(GND), .FRAMEN(FRAMEN),
               .GNTN(GNTN), .IDSEL(IDSEL), .IRDYN(IRDYN),
               .Mst_BE({ Mst_BE[3:0] }), .Mst_BE_Sel(Mst_BE_Sel),
               .Mst_Burst_Req(Mst_Burst_Req), .Mst_LatCntEn(Mst_LatCntEn),
               .Mst_One_Read(Mst_One_Read),
               .Mst_Rd_Term_Sel(Mst_Rd_Term_Sel),
               .Mst_RdAd({ Mst_RdAd[31:0] }),
               .Mst_RdBurst_Done(Mst_RdBurst_Done),
               .Mst_RdData_Valid(Mst_RdData_Valid),
               .Mst_Tabort_Det(Mst_Tabort_Det), .Mst_TTO_Det(Mst_TTO_Det),
               .Mst_Two_Reads(Mst_Two_Reads), .Mst_WrAd({ Mst_WrAd[31:0] }),
               .Mst_WrBurst_Done(Mst_WrBurst_Done),
               .Mst_WrData({ Mst_WrData[31:0] }),
               .Mst_WrData_Rdy(Mst_WrData_Rdy),
               .Mst_WrData_Valid(Mst_WrData_Valid),
               .Mst_Xfer_D1(Mst_Xfer_D1), .PAR(PAR), .PCI_clock(PCI_clock),
               .PCI_Cmd({ PCI_Cmd[3:0] }), .PCI_FRAMEN_D1(PCI_FRAME_D1),
               .PCI_reset(PCI_reset), .PERRN(PERRN), .REQN(REQN), .RSTN(RSTN),
               .SERRN(SERRN), .STOPN(STOPN), .TRDYN(TRDYN), .Usr_Abort(GND),
               .Usr_Addr_WrData({ Usr_Addr_WrData[31:0] }),
               .Usr_Adr_Inc(Usr_Adr_Inc), .Usr_Adr_Valid(Usr_Adr_Valid),
               .Usr_CBE({ Usr_CBE[3:0] }),
               .Usr_Last_Cycle_D1(Usr_Last_Cycle_D1),
               .Usr_MstRdAd_Sel(Usr_MstRdAd_Sel),
               .Usr_MstWrAd_Sel(Usr_MstWrAd_Sel),
               .Usr_RdData({ Usr_RdData[31:0] }),
               .Usr_RdDecode(Usr_RdDecode), .Usr_Rdy(Usr_Rdy),
               .Usr_Read(Usr_Read), .Usr_Select(Usr_Select),
               .Usr_Stop(Usr_Stop), .Usr_WrDecode(Usr_WrDecode),
               .Usr_Write(Usr_Write) );
mux4x0 Rdy_Mux ( .A(Mem_Rdy), .B(CIS_sel), .C(cstschg_rdy), .D(GND), .Q(Usr_Rdy),
              .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[31]  ( .A(mem_RdData[31]), .B(CIS_data[31]),
                   .C(cstschg_regs[31]), .D(GND_bit), .Q(Usr_RdData[31]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[30]  ( .A(mem_RdData[30]), .B(CIS_data[30]),
                   .C(cstschg_regs[30]), .D(GND_bit), .Q(Usr_RdData[30]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[29]  ( .A(mem_RdData[29]), .B(CIS_data[29]),
                   .C(cstschg_regs[29]), .D(GND_bit), .Q(Usr_RdData[29]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[28]  ( .A(mem_RdData[28]), .B(CIS_data[28]),
                   .C(cstschg_regs[28]), .D(GND_bit), .Q(Usr_RdData[28]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[27]  ( .A(mem_RdData[27]), .B(CIS_data[27]),
                   .C(cstschg_regs[27]), .D(GND_bit), .Q(Usr_RdData[27]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[26]  ( .A(mem_RdData[26]), .B(CIS_data[26]),
                   .C(cstschg_regs[26]), .D(GND_bit), .Q(Usr_RdData[26]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[25]  ( .A(mem_RdData[25]), .B(CIS_data[25]),
                   .C(cstschg_regs[25]), .D(GND_bit), .Q(Usr_RdData[25]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[24]  ( .A(mem_RdData[24]), .B(CIS_data[24]),
                   .C(cstschg_regs[24]), .D(GND_bit), .Q(Usr_RdData[24]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[23]  ( .A(mem_RdData[23]), .B(CIS_data[23]),
                   .C(cstschg_regs[23]), .D(GND_bit), .Q(Usr_RdData[23]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[22]  ( .A(mem_RdData[22]), .B(CIS_data[22]),
                   .C(cstschg_regs[22]), .D(GND_bit), .Q(Usr_RdData[22]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[21]  ( .A(mem_RdData[21]), .B(CIS_data[21]),
                   .C(cstschg_regs[21]), .D(GND_bit), .Q(Usr_RdData[21]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[20]  ( .A(mem_RdData[20]), .B(CIS_data[20]),
                   .C(cstschg_regs[20]), .D(GND_bit), .Q(Usr_RdData[20]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[19]  ( .A(mem_RdData[19]), .B(CIS_data[19]),
                   .C(cstschg_regs[19]), .D(GND_bit), .Q(Usr_RdData[19]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[18]  ( .A(mem_RdData[18]), .B(CIS_data[18]),
                   .C(cstschg_regs[18]), .D(GND_bit), .Q(Usr_RdData[18]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[17]  ( .A(mem_RdData[17]), .B(CIS_data[17]),
                   .C(cstschg_regs[17]), .D(GND_bit), .Q(Usr_RdData[17]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[16]  ( .A(mem_RdData[16]), .B(CIS_data[16]),
                   .C(cstschg_regs[16]), .D(GND_bit), .Q(Usr_RdData[16]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[15]  ( .A(mem_RdData[15]), .B(CIS_data[15]),
                   .C(cstschg_regs[15]), .D(GND_bit), .Q(Usr_RdData[15]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[14]  ( .A(mem_RdData[14]), .B(CIS_data[14]),
                   .C(cstschg_regs[14]), .D(GND_bit), .Q(Usr_RdData[14]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[13]  ( .A(mem_RdData[13]), .B(CIS_data[13]),
                   .C(cstschg_regs[13]), .D(GND_bit), .Q(Usr_RdData[13]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[12]  ( .A(mem_RdData[12]), .B(CIS_data[12]),
                   .C(cstschg_regs[12]), .D(GND_bit), .Q(Usr_RdData[12]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[11]  ( .A(mem_RdData[11]), .B(CIS_data[11]),
                   .C(cstschg_regs[11]), .D(GND_bit), .Q(Usr_RdData[11]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[10]  ( .A(mem_RdData[10]), .B(CIS_data[10]),
                   .C(cstschg_regs[10]), .D(GND_bit), .Q(Usr_RdData[10]),
                   .S0(CIS_sel), .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[9]  ( .A(mem_RdData[9]), .B(CIS_data[9]), .C(cstschg_regs[9]),
                  .D(GND_bit), .Q(Usr_RdData[9]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[8]  ( .A(mem_RdData[8]), .B(CIS_data[8]), .C(cstschg_regs[8]),
                  .D(GND_bit), .Q(Usr_RdData[8]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[7]  ( .A(mem_RdData[7]), .B(CIS_data[7]), .C(cstschg_regs[7]),
                  .D(GND_bit), .Q(Usr_RdData[7]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[6]  ( .A(mem_RdData[6]), .B(CIS_data[6]), .C(cstschg_regs[6]),
                  .D(GND_bit), .Q(Usr_RdData[6]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[5]  ( .A(mem_RdData[5]), .B(CIS_data[5]), .C(cstschg_regs[5]),
                  .D(GND_bit), .Q(Usr_RdData[5]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[4]  ( .A(mem_RdData[4]), .B(CIS_data[4]), .C(cstschg_regs[4]),
                  .D(GND_bit), .Q(Usr_RdData[4]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[3]  ( .A(mem_RdData[3]), .B(CIS_data[3]), .C(cstschg_regs[3]),
                  .D(GND_bit), .Q(Usr_RdData[3]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[2]  ( .A(mem_RdData[2]), .B(CIS_data[2]), .C(cstschg_regs[2]),
                  .D(GND_bit), .Q(Usr_RdData[2]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[1]  ( .A(mem_RdData[1]), .B(CIS_data[1]), .C(cstschg_regs[1]),
                  .D(GND_bit), .Q(Usr_RdData[1]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
mux4x0 \Mux_Data[0]  ( .A(mem_RdData[0]), .B(CIS_data[0]), .C(cstschg_regs[0]),
                  .D(GND_bit), .Q(Usr_RdData[0]), .S0(CIS_sel),
                  .S1(RdData_MUX_sel) );
inpad_25um I228 ( .P(pad_CBLOCK_n), .Q(CBLOCK_n) );
inpad_25um I234 ( .P(pad_PWM), .Q(PWM_in) );
inpad_25um I235 ( .P(pad_BAM), .Q(BAM_in) );
inpad_25um I236 ( .P(pad_wp), .Q(wp_ps) );
inpad_25um I237 ( .P(pad_ready), .Q(ready_ps) );
inpad_25um \inpad_bvd[2]  ( .P(pad_bvd[2]), .Q(bvd_ps[2]) );
inpad_25um \inpad_bvd[1]  ( .P(pad_bvd[1]), .Q(bvd_ps[1]) );
inpad_25um I239 ( .P(pad_gwake), .Q(gwake_ps) );
inpad_25um I240 ( .P(pad_intr), .Q(intr_ps) );
inpad_25um I233 ( .P(pad_clk_resume), .Q(clk_resume) );
inpad_25um \CIS_data[31]  ( .P(pad_CIS_data[31]), .Q(CIS_data[31]) );
inpad_25um \CIS_data[30]  ( .P(pad_CIS_data[30]), .Q(CIS_data[30]) );
inpad_25um \CIS_data[29]  ( .P(pad_CIS_data[29]), .Q(CIS_data[29]) );
inpad_25um \CIS_data[28]  ( .P(pad_CIS_data[28]), .Q(CIS_data[28]) );
inpad_25um \CIS_data[27]  ( .P(pad_CIS_data[27]), .Q(CIS_data[27]) );
inpad_25um \CIS_data[26]  ( .P(pad_CIS_data[26]), .Q(CIS_data[26]) );
inpad_25um \CIS_data[25]  ( .P(pad_CIS_data[25]), .Q(CIS_data[25]) );
inpad_25um \CIS_data[24]  ( .P(pad_CIS_data[24]), .Q(CIS_data[24]) );
inpad_25um \CIS_data[23]  ( .P(pad_CIS_data[23]), .Q(CIS_data[23]) );
inpad_25um \CIS_data[22]  ( .P(pad_CIS_data[22]), .Q(CIS_data[22]) );
inpad_25um \CIS_data[21]  ( .P(pad_CIS_data[21]), .Q(CIS_data[21]) );
inpad_25um \CIS_data[20]  ( .P(pad_CIS_data[20]), .Q(CIS_data[20]) );
inpad_25um \CIS_data[19]  ( .P(pad_CIS_data[19]), .Q(CIS_data[19]) );
inpad_25um \CIS_data[18]  ( .P(pad_CIS_data[18]), .Q(CIS_data[18]) );
inpad_25um \CIS_data[17]  ( .P(pad_CIS_data[17]), .Q(CIS_data[17]) );
inpad_25um \CIS_data[16]  ( .P(pad_CIS_data[16]), .Q(CIS_data[16]) );
inpad_25um \CIS_data[15]  ( .P(pad_CIS_data[15]), .Q(CIS_data[15]) );
inpad_25um \CIS_data[14]  ( .P(pad_CIS_data[14]), .Q(CIS_data[14]) );