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# Schematic : View HDL Functional Model clock.vhf clock.cmd_log # XST (Creating Lso File) : clock.lso # xst flow : RunXST clock.syr clock.prj clock.sprj clock.ana clock.stx clock.cmd_log

SCHEMATIC START ; // created by map version G.35 on Sun Dec 18 17:59:00 2005 COMP "cin" LOCATE = SITE "LB" LEVEL 1; COMP "ina" LOCATE = SITE "BANK1" LEVEL 1; COMP "ina" LOCATE = SITE "

Checking Pins and Pin Connections -------------------------------------------------- Checking Schematic: SCHEMATIC1 -------------------------------------------------- Checking Electrical Rules

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 0} { "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Qua

SCHEMATIC START ; // created by map version F.23 on Wed Nov 06 17:38:46 2002 NET "clkb_BUFGP/IBUFG" BEL "clkb_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ; NET "clka_BUFGP/IBUFG" BEL "clka_BUFGP/BUFG.GCLK

Protel Advanced Schematic Annotation Report for 'DAC.Sch' 20:27:14 4-Jan-2002 JP? => JP900 C? => C900 C? => C901 U? => U90

Protel Advanced Schematic Annotation Report for 'GoHT_ISO' 14:03:08 7-Sep-2006 JP? => JP2 JP? => JP6

Protel Advanced Schematic Annotation Report for 'DAC.Sch' 20:27:14 4-Jan-2002 JP? => JP900 C? => C900 C? => C901 U? => U90

Protel Advanced Schematic Annotation Report for 'GoHT_ISO' 14:03:08 7-Sep-2006 JP? => JP2 JP? => JP6

JDF G // Created by Project Navigator ver 1.0 PROJECT ADI_Deserializer_AD9289_RevD DESIGN adi_deserializer_ad9289_revd DEVFAM virtex2 DEVFAMTIME 0 DEVICE xc2v250 DEVICETIME 0 DEVPKG fg256 DEV