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Xinx ISE 官方源代码盘第二章

SCHEMATIC START ;
// created by map version F.23 on Wed Nov 06 17:38:46 2002 
NET "clkb_BUFGP/IBUFG" BEL "clkb_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ;
NET "clka_BUFGP/IBUFG" BEL "clka_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT ;
PIN "dpram_inst/B5.A_pins<53>" = NET "clka_BUFGP" BEL "dpram_inst/B5.A" ;
TIMEGRP "clka" = PIN "dpram_inst/B5.A_pins<53>" ; 
PIN "dpram_inst/B5.B_pins<53>" = NET "clkb_BUFGP" BEL "dpram_inst/B5.B" ;
TIMEGRP "clkb" = PIN "dpram_inst/B5.B_pins<53>" ; 
TIMEGRP "PADS" = PADS ("*") ; 
TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 10 nS  ; 
TS_clka = PERIOD TIMEGRP "clka"  20 nS   HIGH 50.000000 % ;
TS_clkb = PERIOD TIMEGRP "clkb"  20 nS   HIGH 50.000000 % ;
SCHEMATIC END ;