代码搜索：Scan
找到约 10,000 项符合「Scan」的源代码
代码结果 10,000
www.eeworm.com/read/485513/6552143
c tqm8xxl.c
/*
* Handle mapping of the flash memory access routines
* on TQM8xxL based devices.
*
* based on rpxlite.c
*
* Copyright(C) 2001 Kirk Lee
*
* This code is GPLed
*
*/
www.eeworm.com/read/476691/6748340
ini lanexplorer.ini
[window position]
top=-4
left=-4
width=1032
height=748
[panel position]
left_panel=239
right_panel=126
bottom_panel=83
[Dock]
RightDockPanel=alRight
[NBT_IP]
IP1=192.168.0.0
IP2=192.168.0
www.eeworm.com/read/476207/6764188
cpp main.cpp
#include
#include
#include
#include
#include "constant.h"
#include "scanner.h"
using namespace std;
int main(int argc, char * argv[])
{
char fn
www.eeworm.com/read/403820/11508969
vhd keysan.vhd
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY keysan IS
PORT(
clk_scan : IN STD_LOGIC;
keydrv : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END keysan;
ARCHITECTURE behavier OF keysan IS
CO
www.eeworm.com/read/403820/11508988
bak keysan.vhd.bak
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY keysan IS
PORT(
clk_scan : IN STD_LOGIC;
keydrv : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END deysan;
ARCHITECTURE behavier OF keysan IS
CO
www.eeworm.com/read/403292/11519817
vhd keydecoder.vhd
--按键译码
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY keydecoder IS
PORT (keyin :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
keydrv :IN STD_LOGIC_VECT
www.eeworm.com/read/403292/11519829
vhd keyscan.vhd
--键盘扫描
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY keyscan IS
PORT( clk_scan : IN STD_LOGIC; --扫描时钟，100Hz，10ms
keydrv : OUT STD_LOGIC_V
www.eeworm.com/read/403292/11519986
vhd frequency.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity frequency is
port(clk : in std_logic; --系统时钟25M
en : in std_log
www.eeworm.com/read/402018/11543942
vhd codetran.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity codetran is
port(scan_code :in std_logic_vector(7 downto 0);
clk:in std_logic;
www.eeworm.com/read/347507/11660871
c block.c
/*!
*************************************************************************************
* \file block.c
*
* \brief
* Process one block
*
* \author
* Main contributors (see co