frequency.vhd

这是一个通过外部按键来控制发光二极管发光的程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity frequency is
  port(clk   : in std_logic;   --系统时钟25M
       en    : in std_logic;   --系统开关键
	   keyin : IN   STD_LOGIC_VECTOR(1 DOWNTO 0);
	  keydrv : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
       clkout: out std_logic);--用于驱动外部发光二极管的脉冲
end frequency;

architecture rtl of frequency is
  SIGNAL clk_scan   :  STD_LOGIC;
  signal freq       :  std_logic_vector(1 downto 0);

  COMPONENT fp--分频模块
	GENERIC(N:integer);
	PORT(clk   :IN STD_LOGIC;--全局时钟,25M
     	 clkout:out STD_LOGIC);--为键盘扫描提供10ms的时间
  end component;

  COMPONENT keyscan--键盘扫描
  PORT( clk_scan  : IN STD_LOGIC; --扫描时钟，100Hz，10ms
        keydrv    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));  
  END COMPONENT;

 component keydecoder --按键译码
  PORT (keyin       :IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        keydrv      :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
        clk_scan    :IN std_logic;
        clk         :IN std_logic;
        freq: buffer std_logic_vector(1 downto 0));
 END component;

 component fptd --用于调频
  port(freq:in std_logic_vector(1 downto 0);
         en:in std_logic; 
       clk:in std_logic;   --系统时钟25M
       clkout:out std_logic);--用于驱动外部发光二极管的脉冲
 end component;

 begin
u1:fp
generic map(250000)
port map(clk=>clk,clkout=>clk_scan);
u2:keyscan
port map(clk_scan=>clk_scan,keydrv=>keydrv);
u3:keydecoder
port map(keyin=>keyin,keydrv=>keydrv,clk_scan=>clk_scan,clk=>clk,freq=>freq);
u4:fptd
port map(freq=>freq,en=>en,clk=>clk,clkout=>clkout);
end rtl;