keysan.vhd.bak

FPGA EP1C6Q240C8 4*4键盘模块 4*4矩阵键盘

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY keysan IS
PORT(
		clk_scan : IN 	STD_LOGIC;
		keydrv   : OUT	STD_LOGIC_VECTOR(3 DOWNTO 0));
END deysan;
ARCHITECTURE behavier OF keysan IS
	CONSTANT s0: STD_LOGIC_VECTOR(3 DOWNTO 0):="1110";--
	CONSTANT s1: STD_LOGIC_VECTOR(3 DOWNTO 0):="1101";
	CONSTANT s2: STD_LOGIC_VECTOR(3 DOWNTO 0):="1011";
	CONSTANT s3: STD_LOGIC_VECTOR(3 DOWNTO 0):="0111";
	SIGNAL	present_state:STD_LOGIC_VECTOR(3 DOWNTO 0);
	SIGNAL	next_state:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	PROCESS(clk_scan)
	BEGIN
		IF(clk_scan'event and clk_scan='1')	THEN
			present_state<=next_state;
		END IF;
	END PROCESS;
	PROCESS(present_state)
	BEGIN
		CASE present_state IS
			WHEN s0 =>next_state<=s1;
			WHEN s1 =>next_state<=s2;
			WHEN s2 =>next_state<=s3;
			WHEN s3 =>next_state<=s0;
			WHEN OTHERS =>next_state<=s0;
		END CASE;
	END PROCESS;
	keydrv <= present_state;
END behavier;