代码搜索：SW1
找到约 309 项符合「SW1」的源代码
代码结果 309
www.eeworm.com/read/11147/205305
v oc8051_fpga_tb.v
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
module oc8051_fpga_tb;
reg rst, clk, int1, int2, int3;
wire sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out,
www.eeworm.com/read/11147/205323
v oc8051_fpga_tb.v
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
module oc8051_fpga_tb;
reg rst, clk, int1, int2, int3;
wire sw1, sw2, sw3, sw4, int_act;
wire [7:0] p0_out, p1_out,
www.eeworm.com/read/11147/205332
v oc8051_fpga_top.v
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
module oc8051_fpga_top (clk, rst, int1, int2, int3, sw1, sw2, sw3, sw4, int_act, dispout, p0_out, p1_out, p2_out,
www.eeworm.com/read/12574/245580
net demo1.net
[
J2
DB9RA/F
SERIAL1
]
[
J4
IDC40P
IO LINES
]
[
U9
DIP14
74LS04
]
[
SW1
DIP16
BAUD RATE
]
[
U12
DIP16
4040
]
[
U8
DIP16
74LS138
]
[
U
www.eeworm.com/read/17522/736960
hier_info main.hier_info
|main
over_alarm gate_control:inst3.SW0
SW1 => gate_control:inst3.SW1
SW2 => gate_control:inst3.SW2
Clock => fdiv:inst1.clk
F_in => counter:inst.F_IN
dp
www.eeworm.com/read/17889/765405
v 复件 lcd_init(带ＴＰrd05）.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/17889/765413
v lcd_init_0707.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw4,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/17889/765417
v 复件 复件 lcd_init(带ＴＰrd05）.v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/17889/765418
v lcd_init(rb07).v
//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw2,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs
www.eeworm.com/read/476527/1369629
hier_info main.hier_info
|main
over_alarm gate_control:inst3.SW0
SW1 => gate_control:inst3.SW1
SW2 => gate_control:inst3.SW2
Clock => fdiv:inst1.clk
F_in => counter:inst.F_IN
dp