📄 lcd_init_0707.v
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//7.5 dotclk=1/8 clock 3.3M
module lcd_283rb06(cs,sclk,sdi,clock,hsync,vsync,enable,dotclk,
red,green,blue,A,sw4,ce,oe,we,sw1,sdao,sclo,penirq,db18,db19,db20,db21,db22,db23);
output reg cs;
output reg sclk;
output reg sdi;
output reg hsync;
output reg vsync;
output reg enable;
output reg dotclk;
inout reg [5:0] red;
inout reg [5:0] green;
inout reg [5:0] blue;
output reg ce;
output reg oe;
output reg we;
inout reg db18,db19,db20,db21,db22,db23;
reg [32:0]k ;// 数组
output reg [18:0]A;
input sw4;
//input sw3;
input sw1 ;
reg run_one_flag;
reg [1:0] num_wq;
input penirq;
reg reset;
input clock; //27MHz (37ns)
reg [1:0] sck_count;
reg [24:0] bit_transfered;
reg [7:0] id_command;
reg [7:0] id_data;
reg [7:0] id_data_cmd;
reg [15:0] command[52:0];reg [15:0] data[52:0];
reg [15:0] data_temp;
reg able;
reg [5:0] r_temp;
reg [5:0] g_temp;
reg [5:0] b_temp;
reg [8:0] AddressByte;
reg [8:0] DataByte1;
reg [8:0] DataByte2;
reg [8:0] DataByte1_rd;
reg [8:0] DataByte2_rd;
reg [8:0] AddressByte_wq;
reg [8:0] DataByte1_wq;
reg [8:0] DataByte2_wq;
//reg [7:0] data_received;
reg [4:0] main_state,next_state;
parameter IDLE=4'b0001,
START=4'b0010,
DATA1=4'b0100,
STOP=4'b1000;
parameter s1=3'b001,
s2=3'b010,
delay=3'b100;
//clock 37ns
//PIC01=19'h000000, //picture 01 Tianma Logo
//PIC02 =19'h0x012C00, //picture 02 V-colorbar
//PIC03=19'h025800, //picture 03 H-colorbar
//PIC04=19'h038400, //picture 04 Crosstalk
//PIC05 =19'h04B000, //picture 05 flicker
parameter PIC06 =19'h038400;//19'h05DC00; //picture 06 face
//parameter N = 25000;//25000;(if N=25000,then Tsclk=3.88ms)
reg [5:0] i;
reg [6:0] j;
reg [2:0] state;
reg [31:0] count;
reg [31:0] number;
//reg clock2;
reg [1:0] count2;
reg [1:0]test;
//**************reset signal
reg [31:0] count_reset;
initial
count_reset<=0;
always @ (posedge clock)
begin
// if(count_reset>=0 && count_reset<=100)
if(count_reset>=0 && count_reset<=2)
begin
reset<=1;count_reset<=count_reset+1;
end
//else if(count_reset>100 && count_reset<=250100)
else if(count_reset>2&& count_reset<=8)
begin
reset<=0;count_reset<=count_reset+1;
end
else
reset<=1;
end
always @(negedge reset)
begin
if(!reset)
begin
id_command=8'h70; id_data=8'h72;
command[0]=16'he3; data[0]=16'h3008;
command[1]=16'he7; data[1]=16'h0012;
command[2]=16'hef; data[2]=16'h1231;
command[3]=16'h00; data[3]=16'h0001;
command[4]=16'h01; data[4]=16'h0100;
command[5]=16'h02; data[5]=16'h0700;
command[6]=16'h03; data[6]=16'h1030;
command[7]=16'h04; data[7]=16'h0000;
command[8]=16'h08; data[8]=16'h0402;
command[9]=16'h09; data[9]=16'h0000;
command[10]=16'h0a; data[10]=16'h0008;
command[11]=16'h0c; data[11]=16'h0110;
command[12]=16'h0f; data[12]=16'h0000;
command[13]=16'h10; data[13]=16'h0000;
command[14]=16'h11; data[14]=16'h0007;
command[15]=16'h12; data[15]=16'h0000;
command[16]=16'h13; data[16]=16'h0000;
command[17]=16'h10; data[17]=16'h1190;
command[18]=16'h11; data[18]=16'h0227;
command[19]=16'h12; data[19]=16'h001c;
command[20]=16'h13; data[20]=16'h1200;
command[21]=16'h29; data[21]=16'h0025;
command[22]=16'h2b; data[22]=16'h0009;
command[23]=16'h30; data[23]=16'h0100;
command[24]=16'h31; data[24]=16'h0408;
command[25]=16'h32; data[25]=16'h0000;
command[26]=16'h35; data[26]=16'h0103;
command[27]=16'h36; data[27]=16'h1604;
command[28]=16'h37; data[28]=16'h0305;
command[29]=16'h38; data[29]=16'h0004;
command[30]=16'h39; data[30]=16'h0807;
command[31]=16'h3c; data[31]=16'h0401;
command[32]=16'h3d; data[32]=16'h000a;
command[33]=16'h50; data[33]=16'h0000;
command[34]=16'h51; data[34]=16'h00ef;
command[35]=16'h52; data[35]=16'h0000;
command[36]=16'h53; data[36]=16'h013f;
command[37]=16'h60; data[37]=16'ha700;
command[38]=16'h61; data[38]=16'h0001;
command[39]=16'h6a; data[39]=16'h0000;
command[40]=16'h80; data[40]=16'h0000;
command[41]=16'h81; data[41]=16'h0000;
command[42]=16'h82; data[42]=16'h0000;
command[43]=16'h83; data[43]=16'h0000;
command[44]=16'h84; data[44]=16'h0000;
command[45]=16'h85; data[45]=16'h0000;
command[46]=16'h90; data[46]=16'h0010;
command[47]=16'h92; data[47]=16'h0000;
command[48]=16'h93; data[48]=16'h0003;
command[49]=16'h95; data[49]=16'h0110;
command[50]=16'h97; data[50]=16'h0000;
command[51]=16'h98; data[51]=16'h0000;
command[52]=16'h07; data[52]=16'h0133;
end
end
//状态机循环
always @(posedge clock or negedge reset)
if (!reset)
main_state<=IDLE;
else
main_state<=next_state;
always @( clock or reset)
begin
case(main_state)
IDLE:
next_state=START;
START:
if(sck_count==1)
next_state=DATA1;
else
next_state=START;
DATA1:
if(bit_transfered[24]==1 && sck_count==1)
next_state=STOP;
else
next_state=DATA1;
STOP:
if(sck_count==1)
next_state=IDLE;
else
next_state=STOP;
default:
next_state=IDLE;
endcase
end
//时钟分频
always @(posedge clock)
if(main_state==IDLE)
sck_count<=0;
else
sck_count<=sck_count+2'b1;
//generate cs
always @(posedge clock or negedge reset)
if(! reset)
cs<=1;
else
begin
if((main_state==IDLE) ||((state==delay)&&(count>=1))||(able==1))
cs<=1;
else if(main_state==START && sck_count==1)
cs<=0;
else if(main_state==STOP && sck_count==3)
cs<=1;
end
//generate sclk
always @(posedge clock or negedge reset)
if(!reset)
sclk<=1;
else
begin
if(main_state==IDLE||main_state==STOP)
sclk<=1;
else if(sck_count==2)
sclk<=0;
else if(sck_count==0)
sclk<=1;
end
//传输比特计数
always @(posedge clock)
if(main_state==IDLE)
bit_transfered<=25'b0;
else if(main_state==START)
bit_transfered<=25'b0_0000_0001;
else if(sck_count==0)
bit_transfered<={bit_transfered[23:0],bit_transfered[24]};
//spi
always @(posedge clock or negedge reset)
if(! reset)
begin
sdi<=1;
i<=0;
end
else
begin
if(main_state==IDLE)
begin
i<=0;
sdi<=1;
end
else if(main_state==STOP && sck_count==2)
begin
sdi<=1;
i<=0;
end
else if(main_state==DATA1 && sck_count==2)
begin
if(i>=0 &&i<8)
sdi<=id_data_cmd[7-i];
else if(i>=8 && i<=23)
sdi<=data_temp[23-i];
i<=i+2'b1;
end
end
// initial
always @(negedge clock or negedge reset)
if(!reset)
begin
j<=0;
state<=s1;
data_temp<=command[0];
id_data_cmd<=id_command;
count<=0;
number<=0;
able<=0;
end
else
begin
if(j<=52)
begin
if(main_state==START && sck_count==1)
begin
case(state)
s1:
begin
data_temp<=command[j];
state<=s2;
id_data_cmd<=id_command;
end
s2:
begin
id_data_cmd<=id_data;
if(j==16)
begin
number<=40948;// delay 200ms;
state<=delay;
data_temp<=data[j];
j<=j+2'b1;
end
else if(j==18)
begin
number<=10237;//delay 50ms;
state<=delay;
data_temp<=data[j];
j<=j+2'b1;
end
else if(j==19)
begin
number<=10237;//delay 50ms;
state<=delay;
data_temp<=data[j];
j<=j+2'b1;
end
else if(j==22)
begin
number<=10237;//delay 50ms;
state<=delay;
data_temp<=data[j];
j<=j+2'b1;
end
else if(j==52)
begin
state<=s2;
data_temp<=data[j];
j<=j+1;
// able<=1;
end
else begin
state<=s1;
data_temp<=data[j];
j<=j+2'b1;
end end
delay:
begin
if(count<number)
begin
count<=count+2'b1;
state<=delay;
end
else
begin
count<=0;
state<=s1;
end
end
default:
begin
state<=s1;
count<=0;
end
endcase
end
end
else if((j==53 )&& (main_state==STOP)&&(i==0)&&(sck_count==1))
begin
data_temp<=16'hff;
able<=1;
end
end
//1/4
parameter[2:0] S00=2'd0,
S01=2'd1,
S02=2'd2,
S03=2'd3,
S04=3'd4;
reg[1:0] state_dclk,next_state_dclk;
always @ (posedge clock)
begin
if(!reset) state_dclk<=S00;
else state_dclk<= next_state_dclk;
end
always @ (state_dclk)
begin
//default values
next_state_dclk=S00;
case (state_dclk)
S00: begin
next_state_dclk=S01;
dotclk=0;
end
S01: begin
next_state_dclk=S02;
dotclk=0;
end
S02: begin
next_state_dclk=S03;
dotclk=0;
end
S03: begin
next_state_dclk=S04;
dotclk=1;
end
S04: begin
next_state_dclk=S00;
dotclk=1;
end
endcase
end
// dotclk 1/8
/*always @ (posedge clock or negedge reset)
if(! reset)
begin
dotclk <= 1'b0;
num_wq<=0;
end
else
begin
if(num_wq<3)
begin
num_wq<=num_wq+1;
end
else begin dotclk<= ~dotclk;num_wq<=0;end
end
*/
// counter register define
// both h&v counter are 10-bit
reg[9:0] h_counter;
reg[9:0] v_counter;
// h&v max. value define
wire h_max=(h_counter==250);
wire v_max=(v_counter==326);
// BLACK CONTROL
reg [3:0] measure_time;
//==================================
// h counter action
always@(posedge dotclk or negedge reset)
if(! reset)
h_counter<=0;
else
begin
if(h_max)
h_counter<=0;
else
h_counter<=h_counter+1;
end
// v_counter action
always@(posedge dotclk or negedge reset)
if(! reset)
v_counter<=0;
else
begin
if(v_max)
v_counter<=0;
else if(h_max)
v_counter<=v_counter+1;
end
//====================================
always@(posedge dotclk or negedge reset)
if(!reset)
begin
hsync<=1;
vsync<=1;
end
else
begin
// h_sync action
hsync<= ( h_counter>=4);
// v_sync action
vsync<= ( v_counter>=1) ;
end
// enable
always@(negedge dotclk or negedge reset)
if(!reset)
enable<=1;
else
begin
enable<=!((h_counter>=5 && h_counter<=244)&&(v_counter>=2)&&(v_counter<=321) );
end
reg pen_probe;
reg[3:0] touch_time;
reg [31:0] delay_measure_count;
reg [11:0] tpx1;
reg [11:0] tpy1;
reg [11:0] tpx2;
reg [11:0] tpy2;
reg [11:0] tpx3;
reg [11:0] tpy3;
reg [7:0] x3;
reg [7:0] y3;
reg [1:0] state_wq;
//=====================================
//37 *4=148ns
always@(negedge clock or negedge reset)
if(! reset)
begin
A<=PIC06;
oe<=1;
we<=1;
ce<=1;
red[5:0]<=6'bz;
green[5:0]<=6'bz;
blue[5:0]<=6'bz;
pen_probe<=0;
test<=0;
measure_time<=0;
delay_measure_count<=0;
state_wq<=0;
end
//pic 01 red
//pic 02 green
//pic 03 blue
//pic 04 white
//pic 05 black
//pic 06 frame
//pic 07 crosstalk
//pic 08 v_gray(16)
//pic 09 h_gray
//pic 10 face
else
begin
case(pic_num)
1://red
if(!dotclk && state_dclk==S00)
begin
//if(!penirq)
//pen_probe=1;
if(v_counter==1)
begin
oe<=1;
we<=1;
ce<=1;
touch_time<=0;
measure_time<=0;
test<=0;
end
else
if( able
&& (v_counter>=2)&&(v_counter<=321)
&&(h_counter>=5 )&& (h_counter<=244))
begin
//if(!pen_probe)
begin
red[5:0]<=6'h3f;
green[5:0]<=6'h00;
blue[5:0]<=6'h00;
end
//else
// begin
// red[5:0]<=6'h00;
// green[5:0]<=6'h00;
// blue[5:0]<=6'h3f;
// end
touch_time<=0;
end
end
2://green
if(!dotclk && state_dclk==S00)
begin
if( able
&& (v_counter>=2)&&(v_counter<=321)
&&(h_counter>=5) && (h_counter<=244))
begin
red[5:0]<=6'h00;
green[5:0]<=6'h3f;
blue[5:0]<=6'h00;
end
end
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