代码搜索：SW1
找到约 309 项符合「SW1」的源代码
代码结果 309
www.eeworm.com/read/436079/1854971
c rf_blink_led.c
#include "include.h"
//-------------------------------------------------------------------------------------------------------
// Defintions used locally in this file.
#define SW1 RB4
#define SW
www.eeworm.com/read/18055/772399
v hour_counter.v
module hour_counter(
clk,
EN,
SW1,SW2,
hour_data1,hour_data0,
EO
);
output [3:0] hour_data1,hour_data0;
output EO;
input clk,EN;
input SW1,SW2;
reg [3:0]
www.eeworm.com/read/18055/772720
v main.v
module main(
SW3,
SW2,
SW1,
Clock,
alarm,
disp_data,
disp_select
);
input SW3;
input SW2;
input SW1;
input Clock;
output alarm;
output [6:0] disp_data;
output [5:0] disp_select
www.eeworm.com/read/18055/772064
v time_auto_and_set.v
module time_auto_and_set(
CLK,
Timepiece_EN,
TimeSet_EN,
SW1,
SW2,
Day_
www.eeworm.com/read/18055/772717
v time_auto_and_set.v
module time_auto_and_set(
CLK,
Timepiece_EN,
TimeSet_EN,
SW1,
SW2,
Day_
www.eeworm.com/read/463503/7179512
c 键龄.c
#include
unsigned long i=0;
bit j;
void sw1()interrupt 2 using 2
{
j=1;
}
www.eeworm.com/read/320943/13415599
v majority_voter.v
//三人表决器 majority_voter.v
module MAJORITY_VOTER(SW1,SW2,SW3,L3,L4);
output L3,L4;
input SW1,SW2,SW3;
assign L3=(SW1&&SW2)||(SW1&&SW3)||(SW2&&SW3);
assign L4=!L3;
/*and(SW12,SW1,SW2);
and(SW13,SW
www.eeworm.com/read/386605/2570042
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pluse_gen is
port(
clk : in vl_logic;
rst : in vl_logic;
sw1 : in vl_logic
www.eeworm.com/read/386605/2570044
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity timer_top is
port(
clk : in vl_logic;
rst : in vl_logic;
sw1 : in vl_logic
www.eeworm.com/read/18055/772089
hier_info time_auto_and_set.hier_info
|time_auto_and_set
CLK => CLK~0.IN1
Timepiece_EN => Timepiece_EN~0.IN1
TimeSet_EN => TimeSet_EN~0.IN2
SW1 => SW1~0.IN1
SW2 => SW2~0.IN1
Day_EN