代码搜索：STD_LOGIC
找到约 10,000 项符合「STD_LOGIC」的源代码
代码结果 10,000
www.eeworm.com/read/177925/9426911
vhd mcuconnect.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mcuconnect is
port(
--reset: in std_logic;
ALE : in STD_LOGIC; --ale signal
www.eeworm.com/read/168723/9899644
vhd bp2.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity bp2 is
port (clk : in std_logic;
indata : in std_logic;
indatb : in std_lo
www.eeworm.com/read/439412/7710175
vhd lfsr2_vhd.vhd
--
-- Module: SR_16_TAP1
-- Design: 16 bit LFSR using a single instantiated SRL16Es (sequential version)
-- VHDL code:
--
-- Simulation ModelSim EE v5.4c
--
-- Description: Inferring SRL16Es to be
www.eeworm.com/read/245026/12826110
vhd 单片机与慢速器件接口.vhd
---------------------------------------------------------------------------------------------------
--
-- Title : connect
-- Design : delayconnect
-- Author : cl
-- Company :
www.eeworm.com/read/307546/13720576
vhd mcuconnect.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mcuconnect is
port(
--reset: in std_logic;
ALE : in STD_LOGIC; --ale signal
www.eeworm.com/read/229686/14325240
txt cpld.txt
cpld 与8051的总线接口VHDL源码
-------------------------------------------------------------------------------------------
关于系统的说明：
8051工作于11.0592MHZ,RAM扩展为128KB的628128,FlashR
www.eeworm.com/read/221465/14741091
vhd cpldbus51.vhd
--cpld 与8051的总线接口VHDL源码
--8051工作频率为11.0592MHZ CPLD(EPM7128SLC15)的工作频率为16.0000MHZ(有源晶振)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cpldbus51 is
p
www.eeworm.com/read/367488/9745447
vhd cpldbus51.vhd
--cpld 与8051的总线接口VHDL源码
--8051工作频率为11.0592MHZ CPLD(EPM7128SLC15)的工作频率为16.0000MHZ(有源晶振)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity cpldbus51 is
p
www.eeworm.com/read/184494/9099158
txt qiangda1.txt
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
www.eeworm.com/read/182620/9198426
vhd sdh_top.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
entity sdh_transact_top is
port(
rc_clk : in STD_LOGIC; --
reset : in STD_LOGIC;
clk_10m