lfsr2_vhd.vhd

LFSRs as Functional Blocks in Wireless Applications

--
-- Module: 	SR_16_TAP1
-- Design: 	16 bit LFSR using a single instantiated SRL16Es (sequential version)
-- VHDL code:	
--
-- Simulation	ModelSim EE v5.4c
--
-- Description: 	Inferring SRL16Es to be used in LFSRs
--
--
-- Device: 	VIRTEX, VIRTEX-E, Spartan2 Families
--
-- Created by: Stephen Lim / XILINX - VIRTEX Applications
-- Date: August 2, 2000 -- Version: 1.0
--
-- History: 
-- 	1. 
--
--   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
--  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
-------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;

--Include unisim libraries for functional simulation only
--library unisim;
--use UNISIM.vcomponents.all;

entity SR_16_TAP1 is
    port (
        	CLK: in STD_LOGIC;
        	CLK4x: in STD_LOGIC;
        	RESET: in STD_LOGIC;
		DIN: in STD_LOGIC;
		FILL: in STD_LOGIC;
        	DOUT: out STD_LOGIC
    );
end SR_16_TAP1;

architecture SR_16_TAP1_arch of SR_16_TAP1 is

--Declaration of Xilinx primitive
--Synplify users must include a path to their Virtex libary
component SRL16E
 port (
   Q   : out std_logic;
   A0  : in std_logic;
   A1  : in std_logic;
   A2  : in std_logic;
   A3  : in std_logic;
   D   : in std_logic;
   CLK : in std_logic;
   CE  : in std_logic
 );
end component;

signal TAPD: STD_LOGIC;				-- Output of SRL16E
signal D: STD_LOGIC;				-- Input of DFF
signal Q: STD_LOGIC;				-- Output of DFF
signal ADDR: STD_LOGIC_VECTOR(3 downto 0);  --Dynamically changing address lines

begin

-- You must instantitate this Virtex Primitive because we are changing the address lines, thereby
-- changing the length of the shift register
U1: SRL16E port map(Q =>  TAPD, 
		    A3 => ADDR(3),
		    A2 => ADDR(2),
		    A1 => ADDR(1),
		    A0 => ADDR(0),
		    D =>  D,
		    CLK => CLK4x,
		    CE => ADDR(3));

process (clk4x,RESET) begin
	if (RESET = '1') then
		Q <= '1';
	elsif (clk4x'event and clk4x = '1') then
		if (ADDR(3) = '1') then -- Because this bit of the address line only changes one out of every four
						-- clock cycles, this bit is used to preset the output flip flop.
			Q <= '1';
		else
			Q <= D;
		end if;
    	end if;
end process;


D <= NOT (Q XOR TAPD) when (FILL = '0') else DIN; -- Additional logic added so that the user can load in user-defined bits.

--Changes the address on the taps
process (clk4x, RESET) begin
	if  (RESET = '1') then
		ADDR <= "0001";
	elsif (clk4x'event and clk4x = '1') then
	case (ADDR) is			-- Changing the outputs of the shift register to access the correct taps.
		when "0001" => ADDR <= "0010";
		when "0010" => ADDR <= "0100";
		when "0100" => ADDR <= "1111";
 	    when others => ADDR <= "0001";
	end case;
	end if;
end process;

process (clk,RESET) begin  -- This process registers the final output at the chip rate clock cycle.  (not required)
	if (RESET = '1') then
		DOUT <= '0';
	elsif (clk'event and clk = '1') then
		DOUT <= TAPD;
	end if;
end process;
	
end SR_16_TAP1_arch;