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Warning (10268): Verilog HDL information at SPI_Master.v(62): Always Construct contains both blocking and non-blocking assignments Warning (10273): Verilog HDL warning at SPI_Master.v(145): extended

Analysis & Synthesis report for SPI_Master Thu Nov 22 16:41:54 2007 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; -------------------

Extra Info: Performing register packing on registers with non-logic cell location assignments Extra Info: Completed register packing on registers with non-logic cell location assignments Extra Info:

Flow report for SPI_Master Thu Nov 22 16:42:11 2007 Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal N

Fitter Status : Successful - Thu Nov 22 16:42:02 2007 Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version Revision Name : SPI_Master Top-level Entity Name : SPI_Master Family : MAX II D

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}